From: Stephen Warren <swar...@nvidia.com>
The ULPI port is routed onto pins on the mini PCI Express connector. A
standard breakout board may be used to access the port.
* Add required DT entries to configure the ULPI port.
* Setup up the ULPI pinmux in the board code.
* Enable multiple USB controller and ULPI support in the board config.
Signed-off-by: Stephen Warren <swar...@nvidia.com>
---
board/nvidia/dts/tegra20-harmony.dts | 3 ++-
board/nvidia/harmony/harmony.c | 9 +++++++++
include/configs/harmony.h | 3 +++
3 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/board/nvidia/dts/tegra20-harmony.dts
b/board/nvidia/dts/tegra20-harmony.dts
index ca5facb..5645a8d 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -8,6 +8,7 @@
aliases {
usb0 = "/usb@c5008000";
+ usb1 = "/usb@c5004000";
};
memory {
@@ -52,7 +53,7 @@
};
usb@c5004000 {
- status = "disabled";
+ nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
};
nand-controller@70008000 {
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index 32ed9bb..c7590ac 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -75,3 +75,12 @@ int board_mmc_init(bd_t *bd)
return 0;
}
#endif
+
+void pin_mux_usb(void)
+{
+ funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+ pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PINGRP_CDEV2);
+ /* USB2 PHY reset GPIO */
+ pinmux_tristate_disable(PINGRP_UAC);
+}
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d582ae1..040bfe4 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -72,8 +72,11 @@
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
/* USB Host support */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
--
1.7.0.4
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