SDRAM setup alike to ORIGEN Dev board. Signed-off-by: Piotr Wilczek <p.wilc...@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.p...@samsung.com> CC: Minkyu Kang <mk7.k...@samsung.com> Acked-by: Jaehoon Chung <jh80.ch...@samsung.com> --- Changes for v2: - no changes Changes for v3: - no changes Changes for v4: - no changes --- include/configs/trats.h | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/include/configs/trats.h b/include/configs/trats.h index b3b5a3d..151019c 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -190,12 +190,17 @@ #define CONFIG_SYS_HZ 1000 -/* TRATS has 2 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */ -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */ +/* TRATS has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ -- 1.7.5.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
