> Use the newly created mx5 default pin initialization functions in mx5
> board
> files.
>
> Signed-off-by: Benoît Thébaudeau <benoit.thebaud...@advansee.com>
> Cc: Stefano Babic <sba...@denx.de>
Adding missing board maintainers to Cc.
> ---
> .../board/efikamx/efikamx.c | 133
> ++------------------
> .../board/freescale/mx51evk/mx51evk.c | 121
> +-----------------
> .../board/ttcontrol/vision2/vision2.c | 72
> +----------
> 3 files changed, 15 insertions(+), 311 deletions(-)
>
> diff --git u-boot-4d3c95f.orig/board/efikamx/efikamx.c
> u-boot-4d3c95f/board/efikamx/efikamx.c
> index e88b2ed..6810433 100644
> --- u-boot-4d3c95f.orig/board/efikamx/efikamx.c
> +++ u-boot-4d3c95f/board/efikamx/efikamx.c
> @@ -143,38 +143,12 @@ int dram_init(void)
> }
>
> /*
> - * UART configuration
> - */
> -static void setup_iomux_uart(void)
> -{
> - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
> -
> - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
> -}
> -
> -/*
> * SPI configuration
> */
> #ifdef CONFIG_MXC_SPI
> static void setup_iomux_spi(void)
> {
> - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
> + mx51_ecspi1_init_pins();
>
> /* Configure SS0 as a GPIO */
> mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
> @@ -183,16 +157,6 @@ static void setup_iomux_spi(void)
> /* Configure SS1 as a GPIO */
> mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
> gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
> -
> - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> -
> - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
> }
> #else
> static inline void setup_iomux_spi(void) { }
> @@ -333,7 +297,12 @@ int board_mmc_init(bd_t *bis)
> int ret;
> uint32_t cd = efika_mmc_cd();
>
> - /* SDHC1 is used on all revisions, setup control pins first */
> + /* SDHC1 is used on all revisions */
> +
> + /* SDHC1 IOMUX */
> + mx51_esdhc1_init_pins();
> +
> + /* SDHC1 Control lines IOMUX */
> mxc_request_iomux(cd,
> IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> mxc_iomux_set_pad(cd,
> @@ -354,65 +323,8 @@ int board_mmc_init(bd_t *bis)
> /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
> if (machine_is_efikasb() || (machine_is_efikamx() &&
> (get_efika_rev() < EFIKAMX_BOARD_REV_12))) {
> - /* SDHC1 IOMUX */
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> /* SDHC2 IOMUX */
> - mxc_request_iomux(MX51_PIN_SD2_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> + mx51_esdhc2_init_pins();
>
> /* SDHC2 Control lines IOMUX */
> mxc_request_iomux(MX51_PIN_GPIO1_7,
> @@ -436,33 +348,6 @@ int board_mmc_init(bd_t *bis)
> if (!ret)
> ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
> } else { /* New boards use only SDHC1 */
> - /* SDHC1 IOMUX */
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
> }
>
> @@ -676,7 +561,7 @@ int board_early_init_f(void)
> {
> init_drive_strength();
>
> - setup_iomux_uart();
> + mx51_uart1_init_pins();
> setup_iomux_spi();
> setup_iomux_led();
>
> diff --git u-boot-4d3c95f.orig/board/freescale/mx51evk/mx51evk.c
> u-boot-4d3c95f/board/freescale/mx51evk/mx51evk.c
> index 514a7ac..dedfb7e 100644
> --- u-boot-4d3c95f.orig/board/freescale/mx51evk/mx51evk.c
> +++ u-boot-4d3c95f/board/freescale/mx51evk/mx51evk.c
> @@ -60,21 +60,6 @@ int dram_init(void)
> return 0;
> }
>
> -static void setup_iomux_uart(void)
> -{
> - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
> -
> - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
> -}
> -
> static void setup_iomux_fec(void)
> {
> /*FEC_MDIO*/
> @@ -153,29 +138,11 @@ static void setup_iomux_fec(void)
> #ifdef CONFIG_MXC_SPI
> static void setup_iomux_spi(void)
> {
> - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
> -
> - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
> + mx51_ecspi1_init_pins();
>
> /* de-select SS1 of instance: ecspi1. */
> mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
> mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
> -
> - /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
> -
> - /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
> -
> - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
> }
> #endif
>
> @@ -354,90 +321,10 @@ int board_mmc_init(bd_t *bis)
> index++) {
> switch (index) {
> case 0:
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA2,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA3,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_GPIO1_0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
> - PAD_CTL_HYS_ENABLE);
> - mxc_request_iomux(MX51_PIN_GPIO1_1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
> - PAD_CTL_HYS_ENABLE);
> + mx51_esdhc1_init_pins();
> break;
> case 1:
> - mxc_request_iomux(MX51_PIN_SD2_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD2_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD2_DATA0,
> - IOMUX_CONFIG_ALT0);
> - mxc_request_iomux(MX51_PIN_SD2_DATA1,
> - IOMUX_CONFIG_ALT0);
> - mxc_request_iomux(MX51_PIN_SD2_DATA2,
> - IOMUX_CONFIG_ALT0);
> - mxc_request_iomux(MX51_PIN_SD2_DATA3,
> - IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_SD2_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> + mx51_esdhc2_init_pins();
> mxc_request_iomux(MX51_PIN_GPIO1_6,
> IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
> @@ -509,7 +396,7 @@ void lcd_enable(void)
>
> int board_early_init_f(void)
> {
> - setup_iomux_uart();
> + mx51_uart1_init_pins();
> setup_iomux_fec();
> #ifdef CONFIG_USB_EHCI_MX5
> setup_usb_h1();
> diff --git u-boot-4d3c95f.orig/board/ttcontrol/vision2/vision2.c
> u-boot-4d3c95f/board/ttcontrol/vision2/vision2.c
> index d68bef7..a96c475 100644
> --- u-boot-4d3c95f.orig/board/ttcontrol/vision2/vision2.c
> +++ u-boot-4d3c95f/board/ttcontrol/vision2/vision2.c
> @@ -182,21 +182,7 @@ static void setup_uart(void)
> #ifdef CONFIG_MXC_SPI
> void spi_io_init(void)
> {
> - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> + mx51_ecspi1_init_pins();
>
> /*
> * SS1 will be used as GPIO because of uninterrupted
> @@ -212,11 +198,6 @@ void spi_io_init(void)
> mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
> PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> }
>
> static void reset_peripherals(int reset)
> @@ -539,56 +520,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc)
> #ifdef CONFIG_FSL_ESDHC
> int board_mmc_init(bd_t *bis)
> {
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA2,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA3,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_GPIO1_0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
> - PAD_CTL_HYS_ENABLE);
> - mxc_request_iomux(MX51_PIN_GPIO1_1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
> - PAD_CTL_HYS_ENABLE);
> + mx51_esdhc1_init_pins();
>
> return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
> }
>
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