On Wed, Aug 01, 2012 at 10:21:04PM +0200, Andreas Bießmann wrote:
> On 01.08.12 21:28, Markus Hubig wrote:
> > On Wed, Aug 01, 2012 at 11:58:22AM +0200, Andreas Bießmann wrote:
> >>> + /* Need to reset PHY -> 500ms reset */
> >>> + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
> >>> + AT91_RSTC_MR_URSTEN, &rstc->mr);
> >>
> >> Hmm ... is it OK to generate the user reset here? I know this is the
> >> same in at least at91sam9263ek, can you please check if we should
> >> instead delete that bit in MR?
> >
> > MR? Sorry I don't get this one. Please explain a bit ...
>
> I talked about URSTEN bit in RSTC_MR (Reset Controller Mode Register;
> p99 in at91sam9g20 datasheet). The URSTEN bit set to 1 means disable low
> level detection on NRST pin. Which in fact disables external reset with
> the reset key. One have to check if this is true or maybe I'm wrong here.
Hmm ok I'll investigate this a bit further ...
> > | /* avoid shutdown by watchdog */
> > | hw_watchdog_reset();
>
> WATCHDOG_RESET();
Fixed!
> > | if (timeout <= 0) {
> > | debug("ERROR: Timeout waiting for PHY reset!\n");
>
> Error messages should not use debug macro.
Fixed!
> For timeout stuff you could also use get_timer(0) to get current
> timestamp and compare against another timestamp.
Fixed!
Cheers, Markus
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