On 07/31/2012 10:40 AM, Stephen Warren wrote:
> On 07/31/2012 12:21 AM, Thierry Reding wrote:
>> In order for cache invalidation and flushing to work properly, the data
>> and OOB buffers must be aligned to full cache lines.
>>
>> Signed-off-by: Thierry Reding <thierry.red...@avionic-design.de>
>
> You probably want to CC the NAND maintainer, Scott Wood (I have here) so
> he can ack this or apply it.
>
>> ---
>> common/cmd_nand.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/common/cmd_nand.c b/common/cmd_nand.c
>> index a91ccf4..4367f5a 100644
>> --- a/common/cmd_nand.c
>> +++ b/common/cmd_nand.c
>> @@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int
>> only_oob, int repeat)
>>
>> last = off;
>>
>> - datbuf = malloc(nand->writesize);
>> - oobbuf = malloc(nand->oobsize);
>> + datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
>> + oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
>> if (!datbuf || !oobbuf) {
>> puts("No memory for page buffer\n");
>> return 1;
>
Acked-by: Scott Wood <scottw...@freescale.com>
...though I'm still not fond of the idea that every user of an API has
to know whether DMA might be used on the buffer.
-Scott
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