> -----Original Message----- > From: u-boot-boun...@lists.denx.de [mailto:u-boot- > boun...@lists.denx.de] On Behalf Of Karl O. Pinc > Sent: 27 July 2012 10:27 > To: U-Boot@lists.denx.de > Subject: [U-Boot] U-Boot on the POGO-E02 > > Hi, > > I'm trying to get the latest U-Boot on a > Pogoplug (Pink) POGO-E02. I've gotten > so far as to get something to compile and > thought I'd check here to see if I'm on the > right track. > > The pink Pogoplug is a sheevaplug but > with 256M of RAM instead of 1G. > All it needs is a different kwbimage.cfg > file, it's not really a whole new board, > so I've taken pains not to just duplicate > the sheevaplug board but instead to > create a new target with a different > kwbimage. (Is the trick with > CONFIG_SYS_KWD_CONFIG the right > approach?)
Yes > > The appended patch is to the latest U-Boot > release, 2012-04. I'll see about sending > a patch with git as described in the > FAQ if I get something working. > > This patch is not to apply, but I'm > having a problem because the patch > wraps. boards.cfg contains long > lines, and some of the original > source has long lines as well. > What to do? You may send this patch as RFC for review. Regards... Prafulla . . . > > Thanks for the help. > > Karl <k...@meme.com> > Free Software: "You don't pay back, you pay forward." > -- Robert A. Heinlein > > > -----------<snip>------------------ > diff '--exclude=*~' -ruN u-boot-2012.04.orig/board/Marvell/sheevaplug/ > kwbimage-pogoplug_e02.cfg u-boot-2012.04-pogo//board/Marvell/ > sheevaplug/kwbimage-pogoplug_e02.cfg > --- u-boot-2012.04.orig/board/Marvell/sheevaplug/kwbimage- > pogoplug_e02.cfg 1969-12-31 18:00:00.000000000 -0600 > +++ u-boot-2012.04-pogo//board/Marvell/sheevaplug/kwbimage- > pogoplug_e02.cfg 2012-07-26 21:18:10.000000000 -0500 > @@ -0,0 +1,166 @@ > +# > +# (C) Copyright 2009 > +# Marvell Semiconductor <www.marvell.com> > +# Written-by: Prafulla Wadaskar <prafu...@marvell.com> > +# Modified for the POGO-E02 by: Karl O. Pinc <k...@meme.com> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > +# MA 02110-1301 USA > +# > +# This is the kwbimage.cfg file for the Pogoplug (Pink) POGO-E02. > +# It is the same as the sheevaplug image (Sheevaplug Development kit > +# board) except that the sheevaplug has 1G of ram and this has only > +# 256M. > +# > +# Refer doc/README.kwbimage for more details about how-to configure > +# and create kirkwood boot image > +# > + > +# Boot Media configurations > +BOOT_FROM nand > +NAND_ECC_MODE default > +NAND_PAGE_SIZE 0x0800 > + > +# SOC registers configuration using bootrom header extension > +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed > + > +# Configure RGMII-0 interface pad voltage to 1.8V > +DATA 0xFFD100e0 0x1b1b1b9b > + > +#Dram initalization for SINGLE x16 CL=5 @ 400MHz > +DATA 0xFFD01400 0x43000c30 # DDR Configuration register > +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) > +# bit23-14: zero > +# bit24: 1= enable exit self refresh mode on DDR access > +# bit25: 1 required > +# bit29-26: zero > +# bit31-30: 01 > + > +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low > +# bit 4: 0=addr/cmd in smame cycle > +# bit 5: 0=clk is driven during self refresh, we don't care for > APX > +# bit 6: 0=use recommended falling edge of clk for addr/cmd > +# bit14: 0=input buffer always powered up > +# bit18: 1=cpu lock transaction enabled > +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled > bit31=0 > +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, > unbuffered DIMM > +# bit30-28: 3 required > +# bit31: 0=no additional STARTBURST delay > + > +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles > value > +1) > +# bit3-0: TRAS lsbs > +# bit7-4: TRCD > +# bit11- 8: TRP > +# bit15-12: TWR > +# bit19-16: TWTR > +# bit20: TRAS msb > +# bit23-21: 0x0 > +# bit27-24: TRRD > +# bit31-28: TRTP > + > +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) > +# bit6-0: TRFC > +# bit8-7: TR2R > +# bit10-9: TR2W > +# bit12-11: TW2W > +# bit31-13: zero required > + > +DATA 0xFFD01410 0x0000000d # DDR Address Control > +# bit1-0: 10, Cs0width=x2 > +# bit3-2: 11, Cs0size=1Gb > +# bit5-4: 00, Cs1width=nonexistant > +# bit7-6: 00, Cs1size =nonexistant > +# bit9-8: 00, Cs2width=nonexistent > +# bit11-10: 00, Cs2size =nonexistent > +# bit13-12: 00, Cs3width=nonexistent > +# bit15-14: 00, Cs3size =nonexistent > +# bit16: 0, Cs0AddrSel > +# bit17: 0, Cs1AddrSel > +# bit18: 0, Cs2AddrSel > +# bit19: 0, Cs3AddrSel > +# bit31-20: 0 required > + > +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control > +# bit0: 0, OpenPage enabled > +# bit31-1: 0 required > + > +DATA 0xFFD01418 0x00000000 # DDR Operation > +# bit3-0: 0x0, DDR cmd > +# bit31-4: 0 required > + > +DATA 0xFFD0141C 0x00000C52 # DDR Mode > +# bit2-0: 2, BurstLen=2 required > +# bit3: 0, BurstType=0 required > +# bit6-4: 4, CL=5 > +# bit7: 0, TestMode=0 normal > +# bit8: 0, DLL reset=0 normal > +# bit11-9: 6, auto-precharge write recovery ???????????? > +# bit12: 0, PD must be zero > +# bit31-13: 0 required > + > +DATA 0xFFD01420 0x00000040 # DDR Extended Mode > +# bit0: 0, DDR DLL enabled > +# bit1: 0, DDR drive strenght normal > +# bit2: 0, DDR ODT control lsd (disabled) > +# bit5-3: 000, required > +# bit6: 1, DDR ODT control msb, (disabled) > +# bit9-7: 000, required > +# bit10: 0, differential DQS enabled > +# bit11: 0, required > +# bit12: 0, DDR output buffer enabled > +# bit31-13: 0 required > + > +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High > +# bit2-0: 111, required > +# bit3 : 1 , MBUS Burst Chop disabled > +# bit6-4: 111, required > +# bit7 : 0 > +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= > 300MHz > +# bit9 : 0 , no half clock cycle addition to dataout > +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals > +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh > +# bit15-12: 1111 required > +# bit31-16: 0 required > + > +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default > values) > +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default > values) > + > +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 > +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size > +# bit0: 1, Window enabled > +# bit1: 0, Write Protect disabled > +# bit3-2: 00, CS0 hit selected > +# bit23-4: ones, required > +# bit31-24: 0x07, Size (i.e. 2^3x16MB=128MB) > + > +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled > +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled > +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled > + > +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) > +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) > +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above > +# bit3-2: 01, ODT1 active NEVER! > +# bit31-4: zero, required > + > +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control > +DATA 0xFFD01480 0x00000001 # DDR Initialization Control > +#bit0=1, enable DDR init upon this register write > + > +# End of Header extension > +DATA 0x0 0x0 > diff '--exclude=*~' -ruN u-boot-2012.04.orig/boards.cfg u-boot- > 2012.04- > pogo//boards.cfg > --- u-boot-2012.04.orig/boards.cfg 2012-04-21 11:55:26.000000000 > -0500 > +++ u-boot-2012.04-pogo//boards.cfg 2012-07-26 21:23:47.000000000 > > -0500 > @@ -151,6 +151,7 @@ > openrd_base arm arm926ejs openrd > Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE > openrd_client arm arm926ejs openrd > Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT > openrd_ultimate arm arm926ejs openrd > Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE > +pogoplug_e02 arm arm926ejs sheevaplug > Marvell kirkwood sheevaplug:BOARD_IS_POGOPLUG_E02 > rd6281a arm arm926ejs - > Marvell kirkwood > sheevaplug arm arm926ejs - > Marvell kirkwood > dockstar arm arm926ejs - > Seagate kirkwood > diff '--exclude=*~' -ruN u-boot-2012.04.orig/doc/README.pogoplug_e02 > u- > boot-2012.04-pogo//doc/README.pogoplug_e02 > --- u-boot-2012.04.orig/doc/README.pogoplug_e02 1969-12-31 > 18:00:00.000000000 -0600 > +++ u-boot-2012.04-pogo//doc/README.pogoplug_e02 2012-07-26 > 21:50:41.000000000 -0500 > @@ -0,0 +1,47 @@ > +The Pogoplug (Pink) Model POGO-E02 is a consumer product based on the > +Marvell Sheevaplug Developers kit, the sheevaplug board. It differs > +from the Sheevaplug in that where the Sheevaplug has 1G of RAM, the > +Pogoplug POGO-E02 has only 256M of RAM. The Sheevaplug is also a > nice > +small white brick, whereas the POGO-E02 is a pink and white plastic > +monstrosity. The POGO-E02 has no external serial connector and must > +be opened by popping the case to get to the 3.3v serial connector. > + > +Note that there are other Pogoplug models. This will work only > +with the POGO-E02. > + > +Description of the 3.3v serial connector: > + > +When 'gap' in the keyed connector is "up". Pins, left to right are: > + > +3.3v > +TXD > +RXD > +GND > + > +The neighboring connector is a standard 10 pin JTAG. > + > +The serial port may be used to talk to the existing U-Boot command > +interface to obtain the configuration environment and load a new > +U-Boot. (A 3.3v RS232 to USB serial converter is useful here, and > +quite cheap. $2.37, if you're willing to wait for shipping from > +Singapore.) Of course this means you're trusting the factory U-Boot > +code. If you're paranoid use the JTAG interface. > + > +Code for the factory installed U-Boot is at: > + > +http://download.pogoplug.com/opensource/pogoplug-u- > boot-1.1.4.pp2.0.tar.bz2 > + > +The interesting bits are: > + > +dramregs_pp128_A.txt A file which has the 512 byte U-Boot header > + describing how to setup the board. This was > + prepened to the u-boot.img file with > + tools/doimage program. > + > +The change to Das U-Boot is to add a pogoplug_e02 the sheevaplug > +target to support this alternate header. The header is in > +"board/Marvell/sheevaplug/kwbimage-pogoplug_e02.cfg". > + > +See also: doc/README.kwbimage > + > +26 July, 2012 Karl O. Pinc <k...@meme.com> > diff '--exclude=*~' -ruN u-boot-2012.04.orig/include/configs/ > sheevaplug.h u-boot-2012.04-pogo//include/configs/sheevaplug.h > --- u-boot-2012.04.orig/include/configs/sheevaplug.h 2012-04-21 > 11:55:26.000000000 -0500 > +++ u-boot-2012.04-pogo//include/configs/sheevaplug.h 2012-07-26 > 23:34:14.000000000 -0500 > @@ -28,7 +28,11 @@ > /* > * Version number information > */ > +#ifdef CONFIG_BOARD_IS_POGOPLUG_E02 /* Pogoplug (Pink) POGO-E02 > */ > +#define CONFIG_IDENT_STRING "\nPogoplug-POGO-E02" > +#else /* Default: Marvell > Sheevaplug > */ > #define CONFIG_IDENT_STRING "\nMarvell-Sheevaplug" > +#endif /* CONFIG_BOARD_IS_POGOPLUG_E02 */ > > /* > * High Level Configuration Options (easy to change) > @@ -50,6 +54,17 @@ > #define CONFIG_CMD_NAND > #define CONFIG_CMD_PING > #define CONFIG_CMD_USB > + > +/* > + * Kirkwood Data file used to initialize board. > + * (Default, the Sheevaplug Development Kit board, is kwbimage.cfg.) > + * Must be defined before mv-common.h. > + */ > +#ifdef CONFIG_BOARD_IS_POGOPLUG_E02 /* Pogoplug (Pink) POGO-E02 > */ > +/* Different RAM configuration for the POGO-E02. */ > +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage- > pogoplug_e02.cfg > +#endif /* CONFIG_BOARD_IS_POGOPLUG_E02 */ > + > /* > * mv-common.h should be defined after CMD configs since it used them > * to enable certain macros > diff '--exclude=*~' -ruN u-boot-2012.04.orig/MAINTAINERS u- > boot-2012.04-pogo//MAINTAINERS > --- u-boot-2012.04.orig/MAINTAINERS 2012-04-21 11:55:26.000000000 > > -0500 > +++ u-boot-2012.04-pogo//MAINTAINERS 2012-07-26 > 01:16:09.000000000 > -0500 > @@ -769,6 +769,10 @@ > davinci_dm365evm ARM926EJS > davinci_dm6467evm ARM926EJS > > +Karl O. Pinc <k...@meme.com> > + > + pogoplug_e02 ARM926EJS (Kirkwood SoC) > + > Helmut Raiger <helmut.rai...@hale.at> > > tt01 i.MX31 > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
