Hi Michael, On Mon, Jul 9, 2012 at 9:57 AM, Hornung, Michael <mhorn...@init-ka.de> wrote:
> +++ b/board/freescale/mx35pdk/imximage.cfg > > +BOOT_FROM spi Please see the Freescale U-boot, you missed the initialization of the CS5: //WEIM config-CS5 init DCDGEN(1, 4, 0xB8002050, 0x0000d843) DCDGEN(1_1, 4, 0xB8002054, 0x22252521) DCDGEN(1_2, 4, 0xB8002058, 0x22220a00) > +# DDR2 init > +DATA 4 0xB8001010 0x00000304 > +DATA 4 0xB8001010 0x0000030C > +DATA 4 0xB8001004 0x007ffc3f > +DATA 4 0xB8001000 0x92220000 > +DATA 4 0x80000400 0x12345678 > +DATA 4 0xB8001000 0xA2220000 > +DATA 4 0x80000000 0x87654321 > +DATA 4 0x80000000 0x87654321 > +DATA 4 0xB8001000 0xB2220000 > +DATA 1 0x80000233 0xda > +DATA 1 0x82000780 0xda > +DATA 1 0x82000400 0xda > +DATA 4 0xB8001000 0x82226080 > +DATA 4 0xB8001004 0x007ffc3f > +DATA 4 0xB800100C 0x007ffc3f > +DATA 4 0xB8001010 0x00000304 > +DATA 4 0xB8001008 0x00002000 > > > --- a/board/freescale/mx35pdk/lowlevel_init.S > +++ b/board/freescale/mx35pdk/lowlevel_init.S > > init_sdram_start: > /*init_sdram*/ > - setup_sdram > + /* setup_sdram */ > > > And here the result (output on the serial line): > > --------------------------------------------------------------------------------------------------- > U-Boot 2012.04.01-00077-g48bcd18-dirty (Jul 09 2012 - 15:22:31) > > CPU: Freescale i.MX35 rev 2.1 at 532 MHz. > Reset cause: POR > I2C: ready > ---------------------------------------------------------------------------------------------------- > > And that's it, no more output after "I2C: ready". Perhaps you have some > more hints about what to do? Most likely it is because it will try to access the network, but you missed to setup the CS5 as per the Freescale U-boot init sequence. Regards, Fabio Estevam _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
