From: Zhong Hongbo <bocui...@gmail.com>
Signed-off-by: Zhong Hongbo <bocui...@gmail.com>
---
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 26 --------------------------
board/samsung/smdk6400/lowlevel_init.S | 6 +++---
2 files changed, 3 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index b254282..acc6a37 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -53,32 +53,6 @@
#define ELFIN_UART_BASE 0x7F005000
#define ELFIN_TIMER_BASE 0x7F006000
-#define STARTUP_AMDIV 533
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-
-#define STARTUP_PCLKDIV 3
-#define STARTUP_HCLKX2DIV 1
-#define STARTUP_HCLKDIV 1
-#define STARTUP_MPLLDIV 1
-#define STARTUP_APLLDIV 0
-
-#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
- (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
-#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-
-#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_AMDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-
-
#ifndef __ASSEMBLY__
static inline unsigned int s3c64xx_get_base_uart(void)
{
diff --git a/board/samsung/smdk6400/lowlevel_init.S
b/board/samsung/smdk6400/lowlevel_init.S
index 3feb164..7ccee59 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -199,13 +199,13 @@ wait_for_async:
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
- ldr r2, =CLK_DIV_VAL
+ ldr r2, =0x3310
orr r1, r1, r2
str r1, [r0, #0x20]
- ldr r1, =APLL_VAL
+ ldr r1, =0x82150601
str r1, [r0, #0x0c] @ APLL_CON_OFFSET
- ldr r1, =MPLL_VAL
+ ldr r1, =0x82150601
str r1, [r0, #0x10] @ MPLL_CON_OFFSET
/* FOUT of EPLL is 96MHz */
--
1.7.5.4
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