From: Zhong Hongbo <bocui...@gmail.com>

The old s3c64xx timer is not work normal, Adopt s5p time design,
It work perfect.

Signed-off-by: Zhong Hongbo <bocui...@gmail.com>
---
 arch/arm/cpu/arm1176/s3c64xx/timer.c |  195 ++++++++++++++++------------------
 1 files changed, 94 insertions(+), 101 deletions(-)

diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c 
b/arch/arm/cpu/arm1176/s3c64xx/timer.c
index f16a37b..7904d09 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/timer.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c
@@ -1,23 +1,8 @@
 /*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroe...@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <a...@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <ga...@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.ro...@arm.com>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <l...@denx.de>
+ * Copyright (C) 2009 Samsung Electronics
+ * Heungjun Kim <riverful....@samsung.com>
+ * Inki Dae <inki....@samsung.com>
+ * Minkyu Kang <mk7.k...@samsung.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -39,64 +24,29 @@
  */
 
 #include <common.h>
-#include <asm/proc-armv/ptrace.h>
+#include <asm/io.h>
 #include <asm/arch/s3c6400.h>
-#include <div64.h>
-
-static ulong timer_load_val;
+#include <asm/arch/pwm.h>
+#include <pwm.h>
 
-#define PRESCALER      167
+DECLARE_GLOBAL_DATA_PTR;
 
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
-       return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
+static unsigned long get_current_tick(void);
 
 /* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
+static inline struct s3c_timer *s3c_get_base_timer(void)
 {
-       s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-       return timers->TCNTO4;
+       return (struct s3c_timer *)s3c64xx_get_base_timer();
 }
 
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
 int timer_init(void)
 {
-       s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-       /* use PWM Timer 4 because it has no output */
-       /*
-        * We use the following scheme for the timer:
-        * Prescaler is hard fixed at 167, divider at 1/4.
-        * This gives at PCLK frequency 66MHz approx. 10us ticks
-        * The timer is set to wrap after 100s, at 66MHz this obviously
-        * happens after 10,000,000 ticks. A long variable can thus
-        * keep values up to 40,000s, i.e., 11 hours. This should be
-        * enough for most uses:-) Possible optimizations: select a
-        * binary-friendly frequency, e.g., 1ms / 128. Also calculate
-        * the prescaler automatically for other PCLK frequencies.
-        */
-       timers->TCFG0 = PRESCALER << 8;
-       if (timer_load_val == 0) {
-               timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
-               timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
-       }
-
-       /* load value for 10 ms timeout */
-       lastdec = timers->TCNTB4 = timer_load_val;
-       /* auto load, manual update of Timer 4 */
-       timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
-               TCON_4_UPDATE;
+       /* PWM Timer 4 */
+       pwm_init(4, MUX_DIV_2, 0);
+       pwm_config(4, 0, 0);
+       pwm_enable(4);
 
-       /* auto load, start Timer 4 */
-       timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
-       timestamp = 0;
+       reset_timer_masked();
 
        return 0;
 }
@@ -104,57 +54,100 @@ int timer_init(void)
 /*
  * timer without interrupts
  */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
+unsigned long get_timer(unsigned long base)
 {
-       ulong now = read_timer();
+       return get_timer_masked() - base;
+}
 
-       if (lastdec >= now) {
-               /* normal mode */
-               timestamp += lastdec - now;
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+       struct s3c_timer *const timer = s3c_get_base_timer();
+       unsigned long tmo, tmp, count_value;
+
+       count_value = readl(&timer->tcntb4);
+
+       if (usec >= 1000) {
+               /*
+                * if "big" number, spread normalization
+                * to seconds
+                * 1. start to normalize for usec to ticks per sec
+                * 2. find number of "ticks" to wait to achieve target
+                * 3. finish normalize.
+                */
+               tmo = usec / 1000;
+               tmo *= (CONFIG_SYS_HZ * count_value);
+               tmo /= 1000;
        } else {
-               /* we have an overflow ... */
-               timestamp += lastdec + timer_load_val - now;
+               /* else small number, don't kill it prior to HZ multiply */
+               tmo = usec * CONFIG_SYS_HZ * count_value;
+               tmo /= (1000 * 1000);
        }
-       lastdec = now;
 
-       return timestamp;
+       /* get current timestamp */
+       tmp = get_current_tick();
+
+       /* if setting this fordward will roll time stamp */
+       /* reset "advancing" timestamp to 0, set lastinc value */
+       /* else, set advancing stamp wake up time */
+       if ((tmo + tmp + 1) < tmp)
+               reset_timer_masked();
+       else
+               tmo += tmp;
+
+       /* loop till event */
+       while (get_current_tick() < tmo)
+
+               ;       /* nop */
 }
 
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
+void reset_timer_masked(void)
 {
-       /* We overrun in 100s */
-       return (ulong)(timer_load_val / 100);
+       struct s3c_timer *const timer = s3c_get_base_timer();
+
+       /* reset time */
+       gd->lastinc = readl(&timer->tcnto4);
+       gd->tbl = 0;
 }
 
-ulong get_timer_masked(void)
+unsigned long get_timer_masked(void)
 {
-       unsigned long long res = get_ticks();
-       do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
-       return res;
+       struct s3c_timer *const timer = s3c_get_base_timer();
+       unsigned long count_value = readl(&timer->tcntb4);
+
+       return get_current_tick() / count_value;
 }
 
-ulong get_timer(ulong base)
+static unsigned long get_current_tick(void)
 {
-       return get_timer_masked() - base;
+       struct s3c_timer *const timer = s3c_get_base_timer();
+       unsigned long now = readl(&timer->tcnto4);
+       unsigned long count_value = readl(&timer->tcntb4);
+
+       if (gd->lastinc >= now)
+               gd->tbl += gd->lastinc - now;
+       else
+               gd->tbl += gd->lastinc + count_value - now;
+
+       gd->lastinc = now;
+
+       return gd->tbl;
 }
 
-void __udelay(unsigned long usec)
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
 {
-       unsigned long long tmp;
-       ulong tmo;
-
-       tmo = (usec + 9) / 10;
-       tmp = get_ticks() + tmo;        /* get current timestamp */
+       return get_timer(0);
+}
 
-       while (get_ticks() < tmp)/* loop till event */
-                /*NOP*/;
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+       return CONFIG_SYS_HZ;
 }
-- 
1.7.5.4

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