On 05.07.2012 14:11, Yann Vernier wrote: > Leave dram_init_banksize to set up the bank info data. > ram_size was previously uninitialized. Also, generalize > lowlevel assembly to support more RAM options. > > Signed-off-by: Yann Vernier <yann.vern...@orsoc.se> > --- > Changes for v2: > - Update to use CONFIG_SYS_SDRAM_ constants > - Update cm41xx also > - Map SDRAM to match configuration > --- > arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 8 +++----- > board/cm4008/cm4008.c | 5 +++-- > board/cm41xx/cm41xx.c | 5 +++-- > include/configs/cm4008.h | 5 ++--- > include/configs/cm41xx.h | 5 ++--- > 5 files changed, 13 insertions(+), 15 deletions(-) > > diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S > b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S > index e9f1227..df13de6 100644 > --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S > +++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S > @@ -131,11 +131,9 @@ highflash: > * before relocating, we have to setup RAM timing > */ > ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0) > -#if (PHYS_SDRAM_1_SIZE == 0x02000000) > - ldr r2, =0x7fc0000e /* 32MB */ > -#else > - ldr r2, =0x3fc0000e /* 16MB */ > -#endif > + /* 8 column address bits, 4 banks, 32 bits data width */ > + ldr r2, > =((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE-0x10000)<<(22-16) | \ > + (CONFIG_SYS_SDRAM_BASE>>(16-12) | 0x00e))
ugh ... magic. Will it work for every possible setting? How about one setting CONFIG_SYS_SDRAM_BASE != 0x0? I the base address related to register content in any way? Would be great to have a little documentation here why it is shifted that way, unfortunately I can not find a KS8695 spec in the net. Don't get me wrong it is ok to do so. I think it is way better than hard coding the values like before but would be great to understand why it is done that way. Best regards Andreas Bießmann _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
