This function can be overridden at run-time and allows implementors
of new boards based on the i.MX28 chip to fine-tune the memory params.
It is possible to write into the dram_vals array because when the SPL
runs, it is located SRAM. Therefore the location is writable. There is
no possibility of these data to be read-only.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Wolfgang Denk <w...@denx.de>
Cc: Detlev Zundel <d...@denx.de>
Cc: Stefano Babic <sba...@denx.de>
Cc: Fabio Estevam <feste...@gmail.com>
---
arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index 9fa5d29..e17a4d7 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -82,10 +82,18 @@ uint32_t dram_vals[] = {
0x00000000, 0x00010001
};
+void __mx28_adjust_memory_params(uint32_t *dram_vals)
+{
+}
+void mx28_adjust_memory_params(uint32_t *dram_vals)
+ __attribute__((weak, alias("__mx28_adjust_memory_params")));
+
void init_m28_200mhz_ddr2(void)
{
int i;
+ mx28_adjust_memory_params(dram_vals);
+
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
--
1.7.10
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