On Mon, Apr 2, 2012 at 12:11 AM, Prafulla Wadaskar <prafu...@marvell.com>
wrote:
>
>
> I remember there was some delay issue on SATA, since processor in this
platform is running at lower clock, (may be) this could be one of parameter
to be considered.
> May be Albert can have some more inside on this.
>
> Regards..
> Prafulla . . .
Hi Prafulla and hopefully Albert,
1 possibility ruled out, 1 tiny piece improved, 1 major problem still
there, & few questions...
0. Latest code in git shows the same behavior... that isn't the issue...
1. Adjusting some of the timings in drivers/block/mvsata_ide.c has allowed
me to apparently solve a _small_ fraction of the problem. I can now get it
to consistently/reliably honor the 'ide reset' command. (before this
timing adjustment, I would frequently see:
..................................
Pogov4> ide reset
Reset IDE: ide_preinit failed
``````````````````````````````````
... so this is one minor part of it that no longer seems a problem.
2. The two 'no IRQ' errors that I see here still persist:
..................................
Reset IDE: Bus 0: OK Bus 1: OK
Device 0: Model: TOSHIBA MK1655GSX Firm: FG010D Ser#: X9AHTNGQT
Type: Hard Disk
Supports 48-bit addressing
Capacity: 152627.8 MB = 149.0 GB (312581808 x 512)
Error (no IRQ) dev 0 blk 16: status 0x7f
No Powersaving mode 7F
Error (no IRQ) dev 0 blk 0: status 0x7f
Device 1: not available
``````````````````````````````````
These apparently come from common/cmd_ide.c . The offsets shown in the
DEBUG output look to me to be the correct ones, referencing the Marvell
docs.
I can't find a meaning for 'status 0x7f', though.
Again, any ideas or hints of what to examine would be appreciated.
3. Prafulla, could a problem w/ my kwbimage.cfg file cause timing
problems? Could the incorrect SoC identification (showing as a 6281
instead of a 6192) cause a problem due to some registers being misread
somehow?
Regards and thanks,
Dave
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