We need to setup CS0 and CS1 not CS0 and CS0 again.
Signed-off-by: Tom Rini <tr...@ti.com>
---
arch/arm/cpu/armv7/omap3/sdrc.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 91f42c0..f6d9b97 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -180,7 +180,7 @@ void do_sdrc_init(u32 cs, u32 early)
write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
rfr_ctrl, mr);
make_cs1_contiguous();
- write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,
+ write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb,
rfr_ctrl, mr);
#endif
--
1.7.0.4
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