Hi Sughosh, On Thursday, January 12, 2012, Sughosh Ganu <urwithsugh...@gmail.com> wrote: > hi Christian, > > On Thu Jan 12, 2012 at 03:04:37PM +0100, Christian Riesch wrote: >> On Thu, Jan 12, 2012 at 2:53 PM, Sughosh Ganu <urwithsugh...@gmail.com> wrote: >> > On Thu Jan 12, 2012 at 01:03:05PM +0100, Christian Riesch wrote: > > <snip> > >> >> >> >> Since all my tests were successful I wonder what issues did you have >> >> with the cache? Can you describe the problems you had? I think the >> >> difference is that you are booting from NAND and have an OMAP-L138, >> >> whereas I boot from SPI (on the da850evm) or from NOR (on calimain) >> >> and have an AM1808 on both boards, right? >> > >> > Thanks a lot for all the testing. One difference i think we have on >> > these boards and hawkboard, is that on hawkboard, the rbl configures >> > the memory and loads the target image(spl in this case) directly to >> > the ram. Looking at da850evm's lds file, it looks like the spl >> > gets loaded to the sram, configures dram and then copies u-boot to >> > the target load address. >> >> This is only true if the SPL is actually used. Have a closer look at >> my test report, I tested three different methods: >> >> 1) The first test was done with the SPL and yes, here the RBL loads >> the SPL into SRAM, initializes DDR memory and then copies u-boot.bin >> to DDR memory. >> 2) The second test was done with TI's UBL. Here, the RBL loads the UBL >> into SRAM, the UBL initializes DDR memory and then copies u-boot.bin >> to DDR memory. >> 3) The third test was done without SPL and without UBL: Here the DDR >> memory init is in the AIS, so in fact the RBL does memory >> initialization and then RBL loads u-boot.bin to DDR memory. This is >> the same case that you have on the hawkboard (only that you have the >> OMAP-L138 and NAND flash instead) and it works for me regardless of >> your patch. > > Yes, the third case is similar to the one used in hawkboard. I'm not > sure as to why it causes a problem on my board, though i'm not sure > if we can compare the two cases, as we have different rbl's. It > could be that the rbl used on hawkboard initialises the caches, as > the caches are off by default on reset. > > Here are the values i use in my ini file for ddr init. > > [EMIF3DDR] > PLL1CFG0 = 0x15010001 > PLL1CFG1 = 0x00000002 > > DDRPHYC1R = 0x00000043 > SDCR = 0x00134632 > SDTIMR = 0x26492a09 > SDTIMR2 = 0x7d13c722 > SDRCR = 0x00000249 > CLK2XSRC = 0x00000000 >
Just for curiosity, could you please send the full ini file? Thanks, Christian
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