Hi Sughosh
Le 14/01/2012 10:21, Sughosh Ganu a écrit :
hi Albert,
On Sat Jan 14, 2012 at 10:02:16AM +0100, Albert ARIBAUD wrote:
<snip>
/*
- * disable MMU stuff and caches
+ * disable MMU and D cache, and enable I cache.
*/
mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000300 /* clear bits 9:8 ( --RS) */
NAK--this alters the functioning of U-Boot for many boards in ways
unpredictable. If you want to get this specific V change into ARM,
then please also add code to set V in all relevant SoCs, or (better
yet IMO) make "do not set V in cpu_init_crit" a config option and
set it in the relevant SoCs or boards.
Ok, but the problem i have is that i don't have visibility into all
the SoC's out there -- don't know what maps where. So i think it
should be done by people using those specific SOC's. I can add a
config option, and introduce it for my board/SOC. Will that be fine.
For me it is fine: this way, you won't affect code behavior for existing
boards.
In any case, i will split this patch into two, with the cache
flushing part kept separate, as it fixes a real issue on my
board. Will work out the setting of the V bit in a separate patch.
This is a good idea too.
-sughosh
Amicalement,
--
Albert.
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