hi Heiko, On Fri Jan 13, 2012 at 04:06:22PM +0100, Heiko Schocher wrote:
<snip> > > >> mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ > >> > >> /* > >> * disable MMU stuff and caches > >> */ > >> mrc p15, 0, r0, c1, c0, 0 > >> - bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) > >> */ > >> + bic r0, r0, #0x00000300 /* clear bits 9:8 ( --RS) */ > > > > Ok, I read your comment above. > > Hmm.. what should we do with the V-Bit? Is it OK not to clear it for all > cases? The V bit gets set to the value of VINITHI input pin on reset, which is the default value. This setting clears the V bit by default, which shifts the vector table to 0x0. Certain SoC's(e.g omap-l138) don't have any valid memory at 0x0. Hence i think this setting should not be made here, but on a SOC level. > > Tested this patch on the cam_enc_4xx and enbw_cmc board, works fine > on that boards. > > > > >> bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ > >> orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ > >> orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ > > > > Although this is not changed in your patch, the last line makes me > > wonder. The comment says "disable MMU stuff and cached", but actually > > the last line sets bit 12 (I), which means that I-Cache gets enabled > > according to [1]. > > Yes, the last line enables the I-Cache. So we should at least add a > better comment here. I will fix the other comments too in the next version. -sughosh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
