On Tue, Jan 3, 2012 at 5:08 PM, Scott Wood <scottw...@freescale.com> wrote: > > Even on SLC chips, when using an ECC block size of 512 bytes? Or are > you only able to find MLC? > > I looked for a datasheet for a 4K NAND chip, but couldn't find one > readily available from a Google search. Hopefully someone internally > can provide me with the one for the chip we're using. >
Yes, this is SLC. The Micron MT29F8G08ABABAWP is one example. The datasheet is here (sign-up required, unfortunately - I can send a copy if you want): https://www.micron.com/parts/nand-flash/mass-storage/mt29f8g08ababawp On page 93, it says "Minimum required ECC: 4-bit ECC per 540 bytes of data". Maybe there are some 4k parts around that don't have this limitation, but our hardware guy informed me that all of the common (high availability) 4k parts he saw were similar. > > There's also the issue of ECC on the boot page itself -- that has to be > hardware ECC, because there's no software running yet. > True. I guess for random bit-flips, maybe that's just as much a problem as the other blocks/pages? I know that the first block is somewhat "special", in that it's guaranteed not to be bad for some minimum # of P/E cycles; will ECC errors still accumulate the same as any other block? > > AFAIK, we've just been using 1-bit hw ECC. I don't know what NAND chip > was used for testing, or how much stress testing was done. > OK. Thanks for the quick reply Scott! -- Matthew L. Creech _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
