On 11/09/2011 10:18 AM, Marek Vasut wrote:
> Signed-off-by: Marek Vasut <marek.va...@gmail.com>
> Cc: Stefano Babic <sba...@denx.de>
> Cc: Wolfgang Denk <w...@denx.de>
> Cc: Detlev Zundel <d...@denx.de>
> ---
> arch/arm/include/asm/arch-mx28/dma.h | 170 +++++++
> arch/arm/include/asm/arch-mx28/imx-regs.h | 1 +
> arch/arm/include/asm/arch-mx28/regs-apbh.h | 466 +++++++++++++++++++
> drivers/dma/Makefile | 1 +
> drivers/dma/apbh_dma.c | 691
> ++++++++++++++++++++++++++++
> 5 files changed, 1329 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-mx28/dma.h
> create mode 100644 arch/arm/include/asm/arch-mx28/regs-apbh.h
> create mode 100644 drivers/dma/apbh_dma.c
>
> diff --git a/arch/arm/include/asm/arch-mx28/dma.h
> b/arch/arm/include/asm/arch-mx28/dma.h
> new file mode 100644
> index 0000000..7061e7c
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx28/dma.h
> @@ -0,0 +1,170 @@
> +/*
> + * Freescale i.MX28 APBH DMA
> + *
> + * Copyright (C) 2011 Marek Vasut <marek.va...@gmail.com>
> + * on behalf of DENX Software Engineering GmbH
> + *
> + * Based on code from LTIB:
> + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef __DMA_H__
> +#define __DMA_H__
> +
> +#include <linux/list.h>
> +
> +#ifndef CONFIG_ARCH_DMA_PIO_WORDS
> +#define DMA_PIO_WORDS 15
> +#else
> +#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
> +#endif
> +
> +#define MXS_DMA_ALIGNMENT 32
> +
> +/*
> + * MXS DMA channels
> + */
> +enum {
> + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
> + MXS_DMA_CHANNEL_AHB_APBH_SSP1,
> + MXS_DMA_CHANNEL_AHB_APBH_SSP2,
> + MXS_DMA_CHANNEL_AHB_APBH_SSP3,
> + MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
> + MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
> + MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
> + MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
> + MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
> + MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
> + MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
> + MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
> + MXS_DMA_CHANNEL_AHB_APBH_SSP,
> + MXS_MAX_DMA_CHANNELS,
> +};
> +
> +/*
> + * MXS DMA hardware command.
> + *
> + * This structure describes the in-memory layout of an entire DMA command,
> + * including space for the maximum number of PIO accesses. See the
> appropriate
> + * reference manual for a detailed description of what these fields mean to
> the
> + * DMA hardware.
> + */
> +#define MXS_DMA_DESC_COMMAND_MASK 0x3
> +#define MXS_DMA_DESC_COMMAND_OFFSET 0
> +#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
> +#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
> +#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
> +#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
> +#define MXS_DMA_DESC_CHAIN (1 << 2)
> +#define MXS_DMA_DESC_IRQ (1 << 3)
> +#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
> +#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
> +#define MXS_DMA_DESC_DEC_SEM (1 << 6)
> +#define MXS_DMA_DESC_WAIT4END (1 << 7)
> +#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
> +#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
> +#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
> +#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
> +#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
> +#define MXS_DMA_DESC_BYTES_OFFSET 16
> +
> +struct mxs_dma_cmd {
> + unsigned long next;
> + unsigned long data;
> + union {
> + dma_addr_t address;
> + unsigned long alternate;
> + };
> + unsigned long pio_words[DMA_PIO_WORDS];
> +};
> +
> +/*
> + * MXS DMA command descriptor.
> + *
> + * This structure incorporates an MXS DMA hardware command structure, along
> + * with metadata.
> + */
> +#define MXS_DMA_DESC_FIRST (1 << 0)
> +#define MXS_DMA_DESC_LAST (1 << 1)
> +#define MXS_DMA_DESC_READY (1 << 31)
> +
> +struct mxs_dma_desc {
> + struct mxs_dma_cmd cmd;
> + unsigned int flags;
> + dma_addr_t address;
> + void *buffer;
> + struct list_head node;
> +};
> +
> +/**
> + * MXS DMA channel
> + *
> + * This structure represents a single DMA channel. The MXS platform code
> + * maintains an array of these structures to represent every DMA channel in
> the
> + * system (see mxs_dma_channels).
> + */
> +#define MXS_DMA_FLAGS_IDLE 0
> +#define MXS_DMA_FLAGS_BUSY (1 << 0)
> +#define MXS_DMA_FLAGS_FREE 0
> +#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
> +#define MXS_DMA_FLAGS_VALID (1 << 31)
> +
> +struct mxs_dma_chan {
> + const char *name;
> + unsigned long dev;
> + struct mxs_dma_device *dma;
> + unsigned int flags;
> + unsigned int active_num;
> + unsigned int pending_num;
> + struct list_head active;
> + struct list_head done;
> +};
> +
> +/* Hardware management ops */
> +int mxs_dma_enable(int channel);
> +int mxs_dma_disable(int channel);
> +int mxs_dma_reset(int channel);
> +int mxs_dma_freeze(int channel);
> +int mxs_dma_unfreeze(int channel);
> +int mxs_dma_read_semaphore(int channel);
> +int mxs_dma_enable_irq(int channel, int enable);
> +int mxs_dma_irq_is_pending(int channel);
> +int mxs_dma_ack_irq(int channel);
> +
> +/* Channel management ops */
> +int mxs_dma_request(int channel);
> +int mxs_dma_release(int channel);
> +
> +/* Descriptor management ops */
> +struct mxs_dma_desc *mxs_dma_desc_alloc(void);
> +void mxs_dma_desc_free(struct mxs_dma_desc *);
> +
> +unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc);
> +int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc);
> +
> +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
> +
> +int mxs_dma_get_finished(int channel, struct list_head *head);
> +int mxs_dma_finish(int channel, struct list_head *head);
> +
> +int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan);
> +int mxs_dma_go(int chan);
> +
> +int mxs_dma_init(void);
> +
> +#endif /* __DMA_H__ */
> diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h
> b/arch/arm/include/asm/arch-mx28/imx-regs.h
> index 32bfd7e..9561b5e 100644
> --- a/arch/arm/include/asm/arch-mx28/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx28/imx-regs.h
> @@ -23,6 +23,7 @@
> #ifndef __IMX_REGS_H__
> #define __IMX_REGS_H__
>
> +#include <asm/arch/regs-apbh.h>
> #include <asm/arch/regs-base.h>
> #include <asm/arch/regs-bch.h>
> #include <asm/arch/regs-clkctrl.h>
> diff --git a/arch/arm/include/asm/arch-mx28/regs-apbh.h
> b/arch/arm/include/asm/arch-mx28/regs-apbh.h
> new file mode 100644
> index 0000000..a7fa1ec
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx28/regs-apbh.h
> @@ -0,0 +1,466 @@
> +/*
> + * Freescale i.MX28 APBH Register Definitions
> + *
> + * Copyright (C) 2011 Marek Vasut <marek.va...@gmail.com>
> + * on behalf of DENX Software Engineering GmbH
> + *
> + * Based on code from LTIB:
> + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef __REGS_APBH_H__
> +#define __REGS_APBH_H__
> +
> +#include <asm/arch/regs-common.h>
> +
> +#ifndef __ASSEMBLY__
> +struct mx28_apbh_regs {
> + mx28_reg(hw_apbh_ctrl0)
> + mx28_reg(hw_apbh_ctrl1)
> + mx28_reg(hw_apbh_ctrl2)
> + mx28_reg(hw_apbh_channel_ctrl)
> + mx28_reg(hw_apbh_devsel)
> + mx28_reg(hw_apbh_dma_burst_size)
> + mx28_reg(hw_apbh_debug)
> +
> + uint32_t reserved[36];
> +
> + union {
> + struct {
> + mx28_reg(hw_apbh_ch_curcmdar)
> + mx28_reg(hw_apbh_ch_nxtcmdar)
> + mx28_reg(hw_apbh_ch_cmd)
> + mx28_reg(hw_apbh_ch_bar)
> + mx28_reg(hw_apbh_ch_sema)
> + mx28_reg(hw_apbh_ch_debug1)
> + mx28_reg(hw_apbh_ch_debug2)
> + } ch[16];
> + struct {
> + mx28_reg(hw_apbh_ch0_curcmdar)
> + mx28_reg(hw_apbh_ch0_nxtcmdar)
> + mx28_reg(hw_apbh_ch0_cmd)
> + mx28_reg(hw_apbh_ch0_bar)
> + mx28_reg(hw_apbh_ch0_sema)
> + mx28_reg(hw_apbh_ch0_debug1)
> + mx28_reg(hw_apbh_ch0_debug2)
> + mx28_reg(hw_apbh_ch1_curcmdar)
> + mx28_reg(hw_apbh_ch1_nxtcmdar)
> + mx28_reg(hw_apbh_ch1_cmd)
> + mx28_reg(hw_apbh_ch1_bar)
> + mx28_reg(hw_apbh_ch1_sema)
> + mx28_reg(hw_apbh_ch1_debug1)
> + mx28_reg(hw_apbh_ch1_debug2)
> + mx28_reg(hw_apbh_ch2_curcmdar)
> + mx28_reg(hw_apbh_ch2_nxtcmdar)
> + mx28_reg(hw_apbh_ch2_cmd)
> + mx28_reg(hw_apbh_ch2_bar)
> + mx28_reg(hw_apbh_ch2_sema)
> + mx28_reg(hw_apbh_ch2_debug1)
> + mx28_reg(hw_apbh_ch2_debug2)
> + mx28_reg(hw_apbh_ch3_curcmdar)
> + mx28_reg(hw_apbh_ch3_nxtcmdar)
> + mx28_reg(hw_apbh_ch3_cmd)
> + mx28_reg(hw_apbh_ch3_bar)
> + mx28_reg(hw_apbh_ch3_sema)
> + mx28_reg(hw_apbh_ch3_debug1)
> + mx28_reg(hw_apbh_ch3_debug2)
> + mx28_reg(hw_apbh_ch4_curcmdar)
> + mx28_reg(hw_apbh_ch4_nxtcmdar)
> + mx28_reg(hw_apbh_ch4_cmd)
> + mx28_reg(hw_apbh_ch4_bar)
> + mx28_reg(hw_apbh_ch4_sema)
> + mx28_reg(hw_apbh_ch4_debug1)
> + mx28_reg(hw_apbh_ch4_debug2)
> + mx28_reg(hw_apbh_ch5_curcmdar)
> + mx28_reg(hw_apbh_ch5_nxtcmdar)
> + mx28_reg(hw_apbh_ch5_cmd)
> + mx28_reg(hw_apbh_ch5_bar)
> + mx28_reg(hw_apbh_ch5_sema)
> + mx28_reg(hw_apbh_ch5_debug1)
> + mx28_reg(hw_apbh_ch5_debug2)
> + mx28_reg(hw_apbh_ch6_curcmdar)
> + mx28_reg(hw_apbh_ch6_nxtcmdar)
> + mx28_reg(hw_apbh_ch6_cmd)
> + mx28_reg(hw_apbh_ch6_bar)
> + mx28_reg(hw_apbh_ch6_sema)
> + mx28_reg(hw_apbh_ch6_debug1)
> + mx28_reg(hw_apbh_ch6_debug2)
> + mx28_reg(hw_apbh_ch7_curcmdar)
> + mx28_reg(hw_apbh_ch7_nxtcmdar)
> + mx28_reg(hw_apbh_ch7_cmd)
> + mx28_reg(hw_apbh_ch7_bar)
> + mx28_reg(hw_apbh_ch7_sema)
> + mx28_reg(hw_apbh_ch7_debug1)
> + mx28_reg(hw_apbh_ch7_debug2)
> + mx28_reg(hw_apbh_ch8_curcmdar)
> + mx28_reg(hw_apbh_ch8_nxtcmdar)
> + mx28_reg(hw_apbh_ch8_cmd)
> + mx28_reg(hw_apbh_ch8_bar)
> + mx28_reg(hw_apbh_ch8_sema)
> + mx28_reg(hw_apbh_ch8_debug1)
> + mx28_reg(hw_apbh_ch8_debug2)
> + mx28_reg(hw_apbh_ch9_curcmdar)
> + mx28_reg(hw_apbh_ch9_nxtcmdar)
> + mx28_reg(hw_apbh_ch9_cmd)
> + mx28_reg(hw_apbh_ch9_bar)
> + mx28_reg(hw_apbh_ch9_sema)
> + mx28_reg(hw_apbh_ch9_debug1)
> + mx28_reg(hw_apbh_ch9_debug2)
> + mx28_reg(hw_apbh_ch10_curcmdar)
> + mx28_reg(hw_apbh_ch10_nxtcmdar)
> + mx28_reg(hw_apbh_ch10_cmd)
> + mx28_reg(hw_apbh_ch10_bar)
> + mx28_reg(hw_apbh_ch10_sema)
> + mx28_reg(hw_apbh_ch10_debug1)
> + mx28_reg(hw_apbh_ch10_debug2)
> + mx28_reg(hw_apbh_ch11_curcmdar)
> + mx28_reg(hw_apbh_ch11_nxtcmdar)
> + mx28_reg(hw_apbh_ch11_cmd)
> + mx28_reg(hw_apbh_ch11_bar)
> + mx28_reg(hw_apbh_ch11_sema)
> + mx28_reg(hw_apbh_ch11_debug1)
> + mx28_reg(hw_apbh_ch11_debug2)
> + mx28_reg(hw_apbh_ch12_curcmdar)
> + mx28_reg(hw_apbh_ch12_nxtcmdar)
> + mx28_reg(hw_apbh_ch12_cmd)
> + mx28_reg(hw_apbh_ch12_bar)
> + mx28_reg(hw_apbh_ch12_sema)
> + mx28_reg(hw_apbh_ch12_debug1)
> + mx28_reg(hw_apbh_ch12_debug2)
> + mx28_reg(hw_apbh_ch13_curcmdar)
> + mx28_reg(hw_apbh_ch13_nxtcmdar)
> + mx28_reg(hw_apbh_ch13_cmd)
> + mx28_reg(hw_apbh_ch13_bar)
> + mx28_reg(hw_apbh_ch13_sema)
> + mx28_reg(hw_apbh_ch13_debug1)
> + mx28_reg(hw_apbh_ch13_debug2)
> + mx28_reg(hw_apbh_ch14_curcmdar)
> + mx28_reg(hw_apbh_ch14_nxtcmdar)
> + mx28_reg(hw_apbh_ch14_cmd)
> + mx28_reg(hw_apbh_ch14_bar)
> + mx28_reg(hw_apbh_ch14_sema)
> + mx28_reg(hw_apbh_ch14_debug1)
> + mx28_reg(hw_apbh_ch14_debug2)
> + mx28_reg(hw_apbh_ch15_curcmdar)
> + mx28_reg(hw_apbh_ch15_nxtcmdar)
> + mx28_reg(hw_apbh_ch15_cmd)
> + mx28_reg(hw_apbh_ch15_bar)
> + mx28_reg(hw_apbh_ch15_sema)
> + mx28_reg(hw_apbh_ch15_debug1)
> + mx28_reg(hw_apbh_ch15_debug2)
> + };
> + };
> + mx28_reg(hw_apbh_version)
> +};
> +#endif
> +
> +#define APBH_CTRL0_SFTRST (1 << 31)
> +#define APBH_CTRL0_CLKGATE (1 << 30)
> +#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
> +#define APBH_CTRL0_APB_BURST_EN (1 << 28)
> +#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
> +#define APBH_CTRL0_RSVD0_OFFSET 16
> +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
> +#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
> +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
> +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
> +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
> +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
> +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
> +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
> +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
> +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
> +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
> +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
> +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
> +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
> +#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
> +#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
> +
> +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
> +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
> +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
> +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
> +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
> +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
> +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
> +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
> +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
> +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
> +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
> +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
> +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
> +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
> +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
> +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
> +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
> +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
> +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
> +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
> +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
> +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
> +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
> +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
> +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
> +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
> +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
> +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
> +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
> +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
> +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
> +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
> +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
> +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
> +
> +#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
> +#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
> +#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
> +#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
> +#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
> +#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
> +#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
> +#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
> +#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
> +#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
> +#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
> +#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
> +#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
> +#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
> +#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
> +#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
> +#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
> +#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
> +#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
> +#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
> +#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
> +#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
> +#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
> +#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
> +#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
> +#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
> +#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
> +#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
> +#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
> +#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
> +#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
> +#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
> +
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
> +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
> +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
> +
> +#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
> +#define APBH_DEVSEL_CH15_OFFSET 30
> +#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
> +#define APBH_DEVSEL_CH14_OFFSET 28
> +#define APBH_DEVSEL_CH13_MASK (0x3 << 26)
> +#define APBH_DEVSEL_CH13_OFFSET 26
> +#define APBH_DEVSEL_CH12_MASK (0x3 << 24)
> +#define APBH_DEVSEL_CH12_OFFSET 24
> +#define APBH_DEVSEL_CH11_MASK (0x3 << 22)
> +#define APBH_DEVSEL_CH11_OFFSET 22
> +#define APBH_DEVSEL_CH10_MASK (0x3 << 20)
> +#define APBH_DEVSEL_CH10_OFFSET 20
> +#define APBH_DEVSEL_CH9_MASK (0x3 << 18)
> +#define APBH_DEVSEL_CH9_OFFSET 18
> +#define APBH_DEVSEL_CH8_MASK (0x3 << 16)
> +#define APBH_DEVSEL_CH8_OFFSET 16
> +#define APBH_DEVSEL_CH7_MASK (0x3 << 14)
> +#define APBH_DEVSEL_CH7_OFFSET 14
> +#define APBH_DEVSEL_CH6_MASK (0x3 << 12)
> +#define APBH_DEVSEL_CH6_OFFSET 12
> +#define APBH_DEVSEL_CH5_MASK (0x3 << 10)
> +#define APBH_DEVSEL_CH5_OFFSET 10
> +#define APBH_DEVSEL_CH4_MASK (0x3 << 8)
> +#define APBH_DEVSEL_CH4_OFFSET 8
> +#define APBH_DEVSEL_CH3_MASK (0x3 << 6)
> +#define APBH_DEVSEL_CH3_OFFSET 6
> +#define APBH_DEVSEL_CH2_MASK (0x3 << 4)
> +#define APBH_DEVSEL_CH2_OFFSET 4
> +#define APBH_DEVSEL_CH1_MASK (0x3 << 2)
> +#define APBH_DEVSEL_CH1_OFFSET 2
> +#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
> +#define APBH_DEVSEL_CH0_OFFSET 0
> +
> +#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
> +#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
> +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
> +#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
> +#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
> +#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
> +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
> +#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
> +#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
> +#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
> +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
> +#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
> +#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
> +#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
> +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
> +#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
> +#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
> +#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
> +#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
> +#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
> +#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
> +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
> +#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
> +#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
> +#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
> +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
> +#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
> +#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
> +#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
> +#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
> +#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
> +#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
> +
> +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
> +#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
> +#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
> +#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
> +#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
> +#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
> +#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
> +#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
> +#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
> +#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
> +
> +#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
> +#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
> +#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
> +#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
> +#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
> +
> +#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
> +
> +#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
> +#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
> +
> +#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
> +#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
> +
> +#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
> +#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
> +#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
> +#define APBH_CHn_CMD_CMDWORDS_OFFSET 12
> +#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
> +#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
> +#define APBH_CHn_CMD_SEMAPHORE (1 << 6)
> +#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
> +#define APBH_CHn_CMD_NANDLOCK (1 << 4)
> +#define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
> +#define APBH_CHn_CMD_CHAIN (1 << 2)
> +#define APBH_CHn_CMD_COMMAND_MASK 0x3
> +#define APBH_CHn_CMD_COMMAND_OFFSET 0
> +#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
> +#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
> +#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
> +#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
> +
> +#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
> +#define APBH_CHn_BAR_ADDRESS_OFFSET 0
> +
> +#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
> +#define APBH_CHn_SEMA_RSVD2_OFFSET 24
> +#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
> +#define APBH_CHn_SEMA_PHORE_OFFSET 16
> +#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
> +#define APBH_CHn_SEMA_RSVD1_OFFSET 8
> +#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
> +#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
> +
> +#define APBH_CHn_DEBUG1_REQ (1 << 31)
> +#define APBH_CHn_DEBUG1_BURST (1 << 30)
> +#define APBH_CHn_DEBUG1_KICK (1 << 29)
> +#define APBH_CHn_DEBUG1_END (1 << 28)
> +#define APBH_CHn_DEBUG1_SENSE (1 << 27)
> +#define APBH_CHn_DEBUG1_READY (1 << 26)
> +#define APBH_CHn_DEBUG1_LOCK (1 << 25)
> +#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
> +#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
> +#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
> +#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
> +#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
> +#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
> +#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
> +#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
> +#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
> +#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
> +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
> +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
> +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
> +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
> +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
> +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
> +#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
> +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
> +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
> +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
> +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
> +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
> +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
> +#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
> +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
> +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
> +#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
> +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
> +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
> +
> +#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
> +#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
> +#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
> +#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
> +
> +#define APBH_VERSION_MAJOR_MASK (0xff << 24)
> +#define APBH_VERSION_MAJOR_OFFSET 24
> +#define APBH_VERSION_MINOR_MASK (0xff << 16)
> +#define APBH_VERSION_MINOR_OFFSET 16
> +#define APBH_VERSION_STEP_MASK 0xffff
> +#define APBH_VERSION_STEP_OFFSET 0
> +
> +#endif /* __REGS_APBH_H__ */
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index 3d9c9f1..5d864b5 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
> LIB := $(obj)libdma.o
>
> COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
> +COBJS-$(CONFIG_APBH_DMA) += apbh_dma.o
> COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
> COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o
>
> diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
> new file mode 100644
> index 0000000..69a1042
> --- /dev/null
> +++ b/drivers/dma/apbh_dma.c
> @@ -0,0 +1,691 @@
> +/*
> + * Freescale i.MX28 APBH DMA driver
> + *
> + * Copyright (C) 2011 Marek Vasut <marek.va...@gmail.com>
> + * on behalf of DENX Software Engineering GmbH
> + *
> + * Based on code from LTIB:
> + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + */
> +
> +#include <linux/list.h>
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <asm/errno.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/dma.h>
> +
> +static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
> +
> +/*
> + * Test is the DMA channel is valid channel
> + */
> +int mxs_dma_validate_chan(int channel)
> +{
> + struct mxs_dma_chan *pchan;
> +
> + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
> + return -EINVAL;
> +
> + pchan = mxs_dma_channels + channel;
> + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +/*
> + * Enable a DMA channel.
> + *
> + * If the given channel has any DMA descriptors on its active list, this
> + * function causes the DMA hardware to begin processing them.
> + *
> + * This function marks the DMA channel as "busy," whether or not there are
> any
> + * descriptors to process.
> + */
> +int mxs_dma_enable(int channel)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + unsigned int sem;
> + struct mxs_dma_chan *pchan;
> + struct mxs_dma_desc *pdesc;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + pchan = mxs_dma_channels + channel;
> +
> + if (pchan->pending_num == 0) {
> + pchan->flags |= MXS_DMA_FLAGS_BUSY;
> + return 0;
> + }
> +
> + pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
> + if (pdesc == NULL)
> + return -EFAULT;
> +
> + if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
> + if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
> + return 0;
> +
> + sem = mxs_dma_read_semaphore(channel);
> + if (sem == 0)
> + return 0;
> +
> + if (sem == 1) {
> + pdesc = list_entry(pdesc->node.next,
> + struct mxs_dma_desc, node);
> + writel(mxs_dma_cmd_address(pdesc),
> + &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
> + }
> + writel(pchan->pending_num,
> + &apbh_regs->ch[channel].hw_apbh_ch_sema);
> + pchan->active_num += pchan->pending_num;
> + pchan->pending_num = 0;
> + } else {
> + pchan->active_num += pchan->pending_num;
> + pchan->pending_num = 0;
> + writel(mxs_dma_cmd_address(pdesc),
> + &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
> + writel(pchan->active_num,
> + &apbh_regs->ch[channel].hw_apbh_ch_sema);
> + writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
> + &apbh_regs->hw_apbh_ctrl0_clr);
> + }
> +
> + pchan->flags |= MXS_DMA_FLAGS_BUSY;
> + return 0;
> +}
> +
> +/*
> + * Disable a DMA channel.
> + *
> + * This function shuts down a DMA channel and marks it as "not busy." Any
> + * descriptors on the active list are immediately moved to the head of the
> + * "done" list, whether or not they have actually been processed by the
> + * hardware. The "ready" flags of these descriptors are NOT cleared, so they
> + * still appear to be active.
> + *
> + * This function immediately shuts down a DMA channel's hardware, aborting
> any
> + * I/O that may be in progress, potentially leaving I/O hardware in an
> undefined
> + * state. It is unwise to call this function if there is ANY chance the
> hardware
> + * is still processing a command.
> + */
> +int mxs_dma_disable(int channel)
> +{
> + struct mxs_dma_chan *pchan;
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + pchan = mxs_dma_channels + channel;
> +
> + if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
> + return -EINVAL;
> +
> + writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
> + &apbh_regs->hw_apbh_ctrl0_set);
> +
> + pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
> + pchan->active_num = 0;
> + pchan->pending_num = 0;
> + list_splice_init(&pchan->active, &pchan->done);
> +
> + return 0;
> +}
> +
> +/*
> + * Resets the DMA channel hardware.
> + */
> +int mxs_dma_reset(int channel)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + writel(1 << (channel + APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET),
> + &apbh_regs->hw_apbh_channel_ctrl_set);
> +
> + return 0;
> +}
> +
> +/*
> + * Freeze a DMA channel.
> + *
> + * This function causes the channel to continuously fail arbitration for bus
> + * access, which halts all forward progress without losing any state. A call
> to
> + * mxs_dma_unfreeze() will cause the channel to continue its current
> operation
> + * with no ill effect.
> + */
> +int mxs_dma_freeze(int channel)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET),
> + &apbh_regs->hw_apbh_channel_ctrl_set);
> +
> + return 0;
> +}
> +
> +/*
> + * Unfreeze a DMA channel.
> + *
> + * This function reverses the effect of mxs_dma_freeze(), enabling the DMA
> + * channel to continue from where it was frozen.
> + */
> +int mxs_dma_unfreeze(int channel)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET),
> + &apbh_regs->hw_apbh_channel_ctrl_clr);
> +
> + return 0;
> +}
> +
> +/*
> + * Read a DMA channel's hardware semaphore.
> + *
> + * As used by the MXS platform's DMA software, the DMA channel's hardware
> + * semaphore reflects the number of DMA commands the hardware will process,
> but
> + * has not yet finished. This is a volatile value read directly from
> hardware,
> + * so it must be be viewed as immediately stale.
> + *
> + * If the channel is not marked busy, or has finished processing all its
> + * commands, this value should be zero.
> + *
> + * See mxs_dma_append() for details on how DMA command blocks must be
> configured
> + * to maintain the expected behavior of the semaphore's value.
> + */
> +int mxs_dma_read_semaphore(int channel)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + uint32_t tmp;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);
> +
> + tmp &= APBH_CHn_SEMA_PHORE_MASK;
> + tmp >>= APBH_CHn_SEMA_PHORE_OFFSET;
> +
> + return tmp;
> +}
> +
> +/*
> + * Enable or disable DMA interrupt.
> + *
> + * This function enables the given DMA channel to interrupt the CPU.
> + */
> +int mxs_dma_enable_irq(int channel, int enable)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + if (enable)
> + writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
> + &apbh_regs->hw_apbh_ctrl1_set);
> + else
> + writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
> + &apbh_regs->hw_apbh_ctrl1_clr);
> +
> + return 0;
> +}
> +
> +/*
> + * Check if a DMA interrupt is pending.
> + */
> +int mxs_dma_irq_is_pending(int channel)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + uint32_t tmp;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + tmp = readl(&apbh_regs->hw_apbh_ctrl1);
> + tmp |= readl(&apbh_regs->hw_apbh_ctrl2);
> +
> + return (tmp >> channel) & 1;
> +}
> +
> +/*
> + * Clear DMA interrupt.
> + *
> + * The software that is using the DMA channel must register to receive its
> + * interrupts and, when they arrive, must call this function to clear them.
> + */
> +int mxs_dma_ack_irq(int channel)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);
> + writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);
> +
> + return 0;
> +}
> +
> +/*
> + * Request to reserve a DMA channel
> + */
> +int mxs_dma_request(int channel)
> +{
> + struct mxs_dma_chan *pchan;
> +
> + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
> + return -EINVAL;
> +
> + pchan = mxs_dma_channels + channel;
> + if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
> + return -ENODEV;
> +
> + if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
> + return -EBUSY;
> +
> + pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
> + pchan->active_num = 0;
> + pchan->pending_num = 0;
> +
> + INIT_LIST_HEAD(&pchan->active);
> + INIT_LIST_HEAD(&pchan->done);
> +
> + return 0;
> +}
> +
> +/*
> + * Release a DMA channel.
> + *
> + * This function releases a DMA channel from its current owner.
> + *
> + * The channel will NOT be released if it's marked "busy" (see
> + * mxs_dma_enable()).
> + */
> +int mxs_dma_release(int channel)
> +{
> + struct mxs_dma_chan *pchan;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + pchan = mxs_dma_channels + channel;
> +
> + if (pchan->flags & MXS_DMA_FLAGS_BUSY)
> + return -EBUSY;
> +
> + pchan->dev = 0;
> + pchan->active_num = 0;
> + pchan->pending_num = 0;
> + pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
> +
> + return 0;
> +}
> +
> +/*
> + * Allocate DMA descriptor
> + */
> +struct mxs_dma_desc *mxs_dma_desc_alloc(void)
> +{
> + struct mxs_dma_desc *pdesc;
> +
> + pdesc = memalign(MXS_DMA_ALIGNMENT, sizeof(struct mxs_dma_desc));
> +
> + if (pdesc == NULL)
> + return NULL;
> +
> + memset(pdesc, 0, sizeof(*pdesc));
> + pdesc->address = (dma_addr_t)pdesc;
> +
> + return pdesc;
> +};
> +
> +/*
> + * Free DMA descriptor
> + */
> +void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
> +{
> + if (pdesc == NULL)
> + return;
> +
> + free(pdesc);
> +}
> +
> +/*
> + * Return the address of the command within a descriptor.
> + */
> +unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
> +{
> + return desc->address + offsetof(struct mxs_dma_desc, cmd);
> +}
> +
> +/*
> + * Check if descriptor is on a channel's active list.
> + *
> + * This function returns the state of a descriptor's "ready" flag. This flag
> is
> + * usually set only if the descriptor appears on a channel's active list. The
> + * descriptor may or may not have already been processed by the hardware.
> + *
> + * The "ready" flag is set when the descriptor is submitted to a channel by a
> + * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is
> + * cleared when a processed descriptor is moved off the active list by a call
> + * to mxs_dma_finish(). The "ready" flag is NOT cleared if the descriptor is
> + * aborted by a call to mxs_dma_disable().
> + */
> +int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc)
> +{
> + return pdesc->flags & MXS_DMA_DESC_READY;
> +}
> +
> +/*
> + * Add a DMA descriptor to a channel.
> + *
> + * If the descriptor list for this channel is not empty, this function sets
> the
> + * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA
> command so
> + * it will chain to the new descriptor's command.
> + *
> + * Then, this function marks the new descriptor as "ready," adds it to the
> end
> + * of the active descriptor list, and increments the count of pending
> + * descriptors.
> + *
> + * The MXS platform DMA software imposes some rules on DMA commands to
> maintain
> + * important invariants. These rules are NOT checked, but they must be
> carefully
> + * applied by software that uses MXS DMA channels.
> + *
> + * Invariant:
> + * The DMA channel's hardware semaphore must reflect the number of DMA
> + * commands the hardware will process, but has not yet finished.
> + *
> + * Explanation:
> + * A DMA channel begins processing commands when its hardware semaphore
> is
> + * written with a value greater than zero, and it stops processing
> commands
> + * when the semaphore returns to zero.
> + *
> + * When a channel finishes a DMA command, it will decrement its
> semaphore if
> + * the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
> + *
> + * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be
> set,
> + * unless it suits the purposes of the software. For example, one could
> + * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
> + * bit set only in the last one. Then, setting the DMA channel's hardware
> + * semaphore to one would cause the entire series of five commands to be
> + * processed. However, this example would violate the invariant given
> above.
> + *
> + * Rule:
> + * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the
> DMA
> + * channel's hardware semaphore will be decremented EVERY time a command
> is
> + * processed.
> + */
> +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
> +{
> + struct mxs_dma_chan *pchan;
> + struct mxs_dma_desc *last;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + pchan = mxs_dma_channels + channel;
> +
> + pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
> + pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
> +
> + if (!list_empty(&pchan->active)) {
> + last = list_entry(pchan->active.prev, struct mxs_dma_desc,
> + node);
> +
> + pdesc->flags &= ~MXS_DMA_DESC_FIRST;
> + last->flags &= ~MXS_DMA_DESC_LAST;
> +
> + last->cmd.next = mxs_dma_cmd_address(pdesc);
> + last->cmd.data |= MXS_DMA_DESC_CHAIN;
> + }
> + pdesc->flags |= MXS_DMA_DESC_READY;
> + if (pdesc->flags & MXS_DMA_DESC_FIRST)
> + pchan->pending_num++;
> + list_add_tail(&pdesc->node, &pchan->active);
> +
> + return ret;
> +}
> +
> +/*
> + * Retrieve processed DMA descriptors.
> + *
> + * This function moves all the descriptors from the DMA channel's "done"
> list to
> + * the head of the given list.
> + */
> +int mxs_dma_get_finished(int channel, struct list_head *head)
> +{
> + struct mxs_dma_chan *pchan;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + if (head == NULL)
> + return 0;
> +
> + pchan = mxs_dma_channels + channel;
> +
> + list_splice(&pchan->done, head);
> +
> + return 0;
> +}
> +
> +/*
> + * Clean up processed DMA descriptors.
> + *
> + * This function removes processed DMA descriptors from the "active" list.
> Pass
> + * in a non-NULL list head to get the descriptors moved to your list. Pass
> NULL
> + * to get the descriptors moved to the channel's "done" list. Descriptors on
> + * the "done" list can be retrieved with mxs_dma_get_finished().
> + *
> + * This function marks the DMA channel as "not busy" if no unprocessed
> + * descriptors remain on the "active" list.
> + */
> +int mxs_dma_finish(int channel, struct list_head *head)
> +{
> + int sem;
> + struct mxs_dma_chan *pchan;
> + struct list_head *p, *q;
> + struct mxs_dma_desc *pdesc;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(channel);
> + if (ret)
> + return ret;
> +
> + pchan = mxs_dma_channels + channel;
> +
> + sem = mxs_dma_read_semaphore(channel);
> + if (sem < 0)
> + return sem;
> +
> + if (sem == pchan->active_num)
> + return 0;
> +
> + list_for_each_safe(p, q, &pchan->active) {
> + if ((pchan->active_num) <= sem)
> + break;
> +
> + pdesc = list_entry(p, struct mxs_dma_desc, node);
> + pdesc->flags &= ~MXS_DMA_DESC_READY;
> +
> + if (head)
> + list_move_tail(p, head);
> + else
> + list_move_tail(p, &pchan->done);
> +
> + if (pdesc->flags & MXS_DMA_DESC_LAST)
> + pchan->active_num--;
> + }
> +
> + if (sem == 0)
> + pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
> +
> + return 0;
> +}
> +
> +/*
> + * Wait for DMA channel to complete
> + */
> +int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + int ret;
> +
> + ret = mxs_dma_validate_chan(chan);
> + if (ret)
> + return ret;
> +
> + if (mx28_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
> + 1 << chan, timeout)) {
> + ret = -ETIMEDOUT;
> + mxs_dma_reset(chan);
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Execute the DMA channel
> + */
> +int mxs_dma_go(int chan)
> +{
> + uint32_t timeout = 10000;
> + int ret;
> +
> + LIST_HEAD(tmp_desc_list);
> +
> + mxs_dma_enable_irq(chan, 1);
> + mxs_dma_enable(chan);
> +
> + /* Wait for DMA to finish. */
> + ret = mxs_dma_wait_complete(timeout, chan);
> +
> + /* Clear out the descriptors we just ran. */
> + mxs_dma_finish(chan, &tmp_desc_list);
> +
> + /* Shut the DMA channel down. */
> + mxs_dma_ack_irq(chan);
> + mxs_dma_reset(chan);
> + mxs_dma_enable_irq(chan, 0);
> + mxs_dma_disable(chan);
> +
> + return ret;
> +}
> +
> +/*
> + * Initialize the DMA hardware
> + */
> +int mxs_dma_init(void)
> +{
> + struct mx28_apbh_regs *apbh_regs =
> + (struct mx28_apbh_regs *)MXS_APBH_BASE;
> + struct mxs_dma_chan *pchan;
> + int ret, channel;
> +
> + mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
> +
> +#ifdef CONFIG_APBH_DMA_BURST8
> + writel(APBH_CTRL0_AHB_BURST8_EN,
> + &apbh_regs->hw_apbh_ctrl0_set);
> +#else
> + writel(APBH_CTRL0_AHB_BURST8_EN,
> + &apbh_regs->hw_apbh_ctrl0_clr);
> +#endif
> +
> +#ifdef CONFIG_APBH_DMA_BURST
> + writel(APBH_CTRL0_APB_BURST_EN,
> + &apbh_regs->hw_apbh_ctrl0_set);
> +#else
> + writel(APBH_CTRL0_APB_BURST_EN,
> + &apbh_regs->hw_apbh_ctrl0_clr);
> +#endif
> +
> + for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
> + pchan = mxs_dma_channels + channel;
> + pchan->flags = MXS_DMA_FLAGS_VALID;
> +
> + ret = mxs_dma_request(channel);
> +
> + if (ret) {
> + printf("MXS DMA: Can't acquire DMA channel %i\n",
> + channel);
> +
> + goto err;
> + }
> +
> + mxs_dma_reset(channel);
> + mxs_dma_ack_irq(channel);
> + }
> +
> + return 0;
> +
> +err:
> + while (--channel >= 0)
> + mxs_dma_release(channel);
> + return ret;
> +}
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de
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