Signed-off-by: Graeme Russ <graeme.r...@gmail.com>
---
Changes for v2:
- Consolidated patch series
- Fixed remaining checkpatch warnings
- Removed references to CONFIG_SYS_SDRAM_ECC_ENABLE - This was never used
and never will be (sc520 is now end-of-life) and was generating
checkpatch errors because of the inline assembler
arch/x86/cpu/sc520/sc520.c | 2 +-
arch/x86/cpu/sc520/sc520_pci.c | 24 ++++++++++-------
arch/x86/cpu/sc520/sc520_sdram.c | 53 --------------------------------------
arch/x86/cpu/sc520/sc520_ssi.c | 43 +++++++++++++++---------------
arch/x86/cpu/sc520/sc520_timer.c | 4 +-
5 files changed, 39 insertions(+), 87 deletions(-)
diff --git a/arch/x86/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c
index 4892c01..3fe85e7 100644
--- a/arch/x86/cpu/sc520/sc520.c
+++ b/arch/x86/cpu/sc520/sc520.c
@@ -49,7 +49,7 @@ int cpu_init_f(void)
asm("movl $0x2000, %%ecx\n"
"0: pushl %%ecx\n"
"popl %%ecx\n"
- "loop 0b\n": : : "ecx");
+ "loop 0b\n" : : : "ecx");
return x86_cpu_init_f();
}
diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c
index e26793a..a13798f 100644
--- a/arch/x86/cpu/sc520/sc520_pci.c
+++ b/arch/x86/cpu/sc520/sc520_pci.c
@@ -70,26 +70,28 @@ int pci_sc520_set_irq(int pci_pin, int irq)
debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
- if (irq < 0 || irq > 15) {
+ if (irq < 0 || irq > 15)
return -1; /* illegal irq */
- }
- if (pci_pin < 0 || pci_pin > 15) {
+ if (pci_pin < 0 || pci_pin > 15)
return -1; /* illegal pci int pin */
- }
/* first disable any non-pci interrupt source that use
* this level */
/* PCI interrupt mapping (A through D)*/
- for (i=0; i<=3 ;i++) {
- if (readb(&sc520_mmcr->pci_int_map[i]) ==
sc520_irq[irq].priority)
+ for (i = 0; i <= 3 ; i++) {
+ tmpb = readb(&sc520_mmcr->pci_int_map[i]);
+
+ if (tmpb == sc520_irq[irq].priority)
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
}
/* GP IRQ interrupt mapping */
- for (i=0; i<=10 ;i++) {
- if (readb(&sc520_mmcr->gp_int_map[i]) ==
sc520_irq[irq].priority)
+ for (i = 0; i <= 10 ; i++) {
+ tmpb = readb(&sc520_mmcr->gp_int_map[i]);
+
+ if (tmpb == sc520_irq[irq].priority)
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
}
@@ -102,10 +104,12 @@ int pci_sc520_set_irq(int pci_pin, int irq)
if (pci_pin < 4) {
/* PCI INTA-INTD */
/* route the interrupt */
- writeb(sc520_irq[irq].priority,
&sc520_mmcr->pci_int_map[pci_pin]);
+ writeb(sc520_irq[irq].priority,
+ &sc520_mmcr->pci_int_map[pci_pin]);
} else {
/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
- writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin
- 4]);
+ writeb(sc520_irq[irq].priority,
+ &sc520_mmcr->gp_int_map[pci_pin - 4]);
/* also set the polarity in this case */
tmpw = readw(&sc520_mmcr->intpinpol);
diff --git a/arch/x86/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c
index 57e4e7d..9dc1334 100644
--- a/arch/x86/cpu/sc520/sc520_sdram.c
+++ b/arch/x86/cpu/sc520/sc520_sdram.c
@@ -40,9 +40,6 @@ static void sc520_set_dram_timing(void);
static void sc520_set_dram_refresh_rate(void);
static void sc520_enable_dram_refresh(void);
static void sc520_enable_sdram(void);
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-static void sc520_enable_ecc(void)
-#endif
int dram_init_f(void)
{
@@ -51,9 +48,6 @@ int dram_init_f(void)
sc520_set_dram_refresh_rate();
sc520_enable_dram_refresh();
sc520_enable_sdram();
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
- sc520_enable_ecc();
-#endif
return 0;
}
@@ -426,53 +420,6 @@ static void sc520_sizemem(void)
writel(0x00000000, &sc520_mmcr->par[4]);
}
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-static void sc520_enable_ecc(void)
-
- /* A nominal memory test: just a byte at each address line */
- movl %eax, %ecx
- shrl $0x1, %ecx
- movl $0x1, %edi
-memtest0:
- movb $0xa5, (%edi)
- cmpb $0xa5, (%edi)
- jne out
- shrl $0x1, %ecx
- andl %ecx, %ecx
- jz set_ecc
- shll $0x1, %edi
- jmp memtest0
-
-set_ecc:
- /* clear all ram with a memset */
- movl %eax, %ecx
- xorl %esi, %esi
- xorl %edi, %edi
- xorl %eax, %eax
- shrl $0x2, %ecx
- cld
- rep stosl
-
- /* enable read, write buffers */
- movb $0x11, %al
- movl $DBCTL, %edi
- movb %al, (%edi)
-
- /* enable NMI mapping for ECC */
- movl $ECCINT, %edi
- movb $0x10, %al
- movb %al, (%edi)
-
- /* Turn on ECC */
- movl $ECCCTL, %edi
- movb $0x05, %al
- movb %al,(%edi)
-
-out:
- jmp init_ecc_ret
-}
-#endif
-
int dram_init(void)
{
ulong dram_ctrl;
diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c
index 3a6a858..cc601e5 100644
--- a/arch/x86/cpu/sc520/sc520_ssi.c
+++ b/arch/x86/cpu/sc520/sc520_ssi.c
@@ -28,37 +28,33 @@
int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
{
- u8 temp=0;
+ u8 temp = 0;
- if (freq >= 8192) {
+ if (freq >= 8192)
temp |= CTL_CLK_SEL_4;
- } else if (freq >= 4096) {
+ else if (freq >= 4096)
temp |= CTL_CLK_SEL_8;
- } else if (freq >= 2048) {
+ else if (freq >= 2048)
temp |= CTL_CLK_SEL_16;
- } else if (freq >= 1024) {
+ else if (freq >= 1024)
temp |= CTL_CLK_SEL_32;
- } else if (freq >= 512) {
+ else if (freq >= 512)
temp |= CTL_CLK_SEL_64;
- } else if (freq >= 256) {
+ else if (freq >= 256)
temp |= CTL_CLK_SEL_128;
- } else if (freq >= 128) {
+ else if (freq >= 128)
temp |= CTL_CLK_SEL_256;
- } else {
+ else
temp |= CTL_CLK_SEL_512;
- }
- if (!lsb_first) {
+ if (!lsb_first)
temp |= MSBF_ENB;
- }
- if (inv_clock) {
+ if (inv_clock)
temp |= CLK_INV_ENB;
- }
- if (inv_phase) {
+ if (inv_phase)
temp |= PHS_INV_ENB;
- }
writeb(temp, &sc520_mmcr->ssictl);
@@ -68,9 +64,11 @@ int ssi_set_interface(int freq, int lsb_first, int
inv_clock, int inv_phase)
u8 ssi_txrx_byte(u8 data)
{
writeb(data, &sc520_mmcr->ssixmit);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
return readb(&sc520_mmcr->ssircv);
}
@@ -78,15 +76,18 @@ u8 ssi_txrx_byte(u8 data)
void ssi_tx_byte(u8 data)
{
writeb(data, &sc520_mmcr->ssixmit);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
}
u8 ssi_rx_byte(void)
{
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+ while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
+ ;
return readb(&sc520_mmcr->ssircv);
}
diff --git a/arch/x86/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c
index 05bc9c1..495a694 100644
--- a/arch/x86/cpu/sc520/sc520_timer.c
+++ b/arch/x86/cpu/sc520/sc520_timer.c
@@ -38,7 +38,7 @@ void sc520_timer_isr(void)
int timer_init(void)
{
/* Register the SC520 specific timer interrupt handler */
- register_timer_isr (sc520_timer_isr);
+ register_timer_isr(sc520_timer_isr);
/* Install interrupt handler for GP Timer 1 */
irq_install_handler (0, timer_isr, NULL);
@@ -62,7 +62,7 @@ int timer_init(void)
writew(100, &sc520_mmcr->gptmr1maxcmpa);
writew(0xe009, &sc520_mmcr->gptmr1ctl);
- unmask_irq (0);
+ unmask_irq(0);
/* Clear the GP Timer 1 status register to get the show rolling*/
writeb(0x02, &sc520_mmcr->gptmrsta);
--
1.7.5.2.317.g391b14
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