On Monday, October 03, 2011 19:54:55 Anton Staaf wrote: > The cache line alignment issue has gone around a couple of times now. This > patch set implements all of the details that we have discussed about the > implementation of ALLOC_CACHE_ALIGN_BUFFER other than the switch to the > Linux style L1_CACHE_BYTES, L1_CACHE_SHIFT, and ARCH_DMA_MINALIGN defines > mentioned by Mike Frysinger. It also includes patches that use the macro > to fix MMC and ext2 buffers, as well as define the > CONFIG_SYS_CACHELINE_SIZE value for Tegra and add a default value for > CONFIG_SYS_CACHELINE_SIZE with a warning if it is used. > > About the Linux defines that Mike suggests. It may make sense to move > these patches over to use that mechanism, especially since there are only > a few configs that define CONFIG_SYS_CACHELINE_SIZE anyway. Also, since > this is an architecture specific parameter and not a board specific one it > makes sense that these configs would be architecture specific. I am also > not supper happy with the fact that most boards generate a warning with > this patchset, because they don't set CONFIG_SYS_CACHELINE_SIZE. But I'm > not sure that silently providing a default is a good idea.
this looks good to me. my only complaint really has nothing to do with this patchset, but with CONFIG_SYS_CACHELINE_SIZE and the L1_CACHE_xxx defines. but we can address that separately since the current law of the land in u-boot appears to be CONFIG_SYS_CACHELINE_SIZE. -mike
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