Flush the dcache before removing the TLB with caches enabled.
Otherwise this might lead to problems later on, e.g. while booting
Linux (as seen on ICON-440SPe).
Signed-off-by: Stefan Roese <s...@denx.de>
---
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 95df1d9..4a2f337 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -657,6 +657,13 @@ phys_size_t initdram(int board_type)
#endif
/*
+ * Flush the dcache before removing the TLB with caches
+ * enabled. Otherwise this might lead to problems later on,
+ * e.g. while booting Linux (as seen on ICON-440SPe).
+ */
+ flush_dcache();
+
+ /*
* Now after initialization (auto-calibration and ECC generation)
* remove the TLB entries with caches enabled and program again with
* desired cache functionality
--
1.7.6.1
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
