Hi Lei, On 08/19/2011 06:31 PM, Lei Wen wrote: > Hi Hong, > > On Fri, Aug 19, 2011 at 5:23 PM, Hong Xu<hong...@atmel.com> wrote: >> Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations >> into this file. >> >> Signed-off-by: Hong Xu<hong...@atmel.com> >> Tested-by: Elen Song<elen.s...@atmel.com> >> CC: Albert Aribaud<albert.u.b...@aribaud.net> >> --- >> Since V1 >> Modified copyright line >> Fix for compiling warnings >> Changed the way to use CONFIG_SYS_CACHELINE_SIZE >> When unaligned buffer detected, emit ERROR instead of WARNING >> >> Do not make a common v5,v6 cache file. It seems arm946 is lack of >> Test-and-Clean DCache operation. And maybe more differents... >> >> arch/arm/cpu/arm926ejs/Makefile | 2 +- >> arch/arm/cpu/arm926ejs/cache.c | 135 >> +++++++++++++++++++++++++++++++++++++++
[..] >> +#include<common.h> >> + >> +#define FLUSH_CACHE_OP 0 >> +#define INVALIDATE_CACHE_OP 1 >> + >> +#ifndef CONFIG_SYS_CACHELINE_SIZE >> +/* >> + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9 >> + * only b'10, aka. 32 bytes cache line len is valid >> + */ >> +#define CONFIG_SYS_CACHELINE_SIZE 32 > > I think we shouldn't make such assumption here. > You could refer to Lukasz's patch over armv7: > http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/105772 > And you also should export one method as: get_dcache_line_size(), so > that we could malloc cache aligned buffer in mmc.c. There was a long loop about this, see http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105113/focus=105137 I agree we may need something like get_dcache_line_size(). This will make driver sane if CONFIG_SYS_CACHELINE_SIZE is not defined. BR, Eric > Best regards, > Lei _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
