Hi Hong, On Fri, Aug 19, 2011 at 5:23 PM, Hong Xu <hong...@atmel.com> wrote: > Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations > into this file. > > Signed-off-by: Hong Xu <hong...@atmel.com> > Tested-by: Elen Song <elen.s...@atmel.com> > CC: Albert Aribaud <albert.u.b...@aribaud.net> > --- > Since V1 > Modified copyright line > Fix for compiling warnings > Changed the way to use CONFIG_SYS_CACHELINE_SIZE > When unaligned buffer detected, emit ERROR instead of WARNING > > Do not make a common v5,v6 cache file. It seems arm946 is lack of > Test-and-Clean DCache operation. And maybe more differents... > > arch/arm/cpu/arm926ejs/Makefile | 2 +- > arch/arm/cpu/arm926ejs/cache.c | 135 > +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 136 insertions(+), 1 deletions(-) > create mode 100644 arch/arm/cpu/arm926ejs/cache.c > > diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile > index 930e0d1..5b5f330 100644 > --- a/arch/arm/cpu/arm926ejs/Makefile > +++ b/arch/arm/cpu/arm926ejs/Makefile > @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk > LIB = $(obj)lib$(CPU).o > > START = start.o > -COBJS = cpu.o > +COBJS = cpu.o cache.o > > SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) > OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c > new file mode 100644 > index 0000000..756c9b1 > --- /dev/null > +++ b/arch/arm/cpu/arm926ejs/cache.c > @@ -0,0 +1,135 @@ > +/* > + * (C) Copyright 2011 Atmel Corporation > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > + > +#define FLUSH_CACHE_OP 0 > +#define INVALIDATE_CACHE_OP 1 > + > +#ifndef CONFIG_SYS_CACHELINE_SIZE > +/* > + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9 > + * only b'10, aka. 32 bytes cache line len is valid > + */ > +#define CONFIG_SYS_CACHELINE_SIZE 32
I think we shouldn't make such assumption here. You could refer to Lukasz's patch over armv7: http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/105772 And you also should export one method as: get_dcache_line_size(), so that we could malloc cache aligned buffer in mmc.c. Best regards, Lei _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
