From: Alexey Minnekhanov <[email protected]> In the future we will need to specify flags for each GDSC for it to function properly. Copy flags field from respective Linux GCC driver.
Turns out, even among SDM845 not all GDSCs are the same. Some of GDSCs do specify the POLL_CFG_GDSCR flag that changes the logic to check the ON/OFF status, other don't. Some qcom clock drivers in U-Boot don't specify any GDSCs at all (apq8016, apq8096, ipq*, qcs404), or GDSCs in their linux GCC driver do not have any flags (qcs615, qcm2290, sm6115, sm7150, sm8250) thus making them unaffected by this change. Add flags to all currently present qcom clock drivers that do need this change (milos, qcs8300, sa8775p, sc7280, sdm670, sdm845, sm6125, sm6350, sm8150, sm8550, sm8650, x1e80100). Signed-off-by: Alexey Minnekhanov <[email protected]> Co-developed-by: Luca Weiss <[email protected]> Signed-off-by: Luca Weiss <[email protected]> --- drivers/clk/qcom/clock-milos.c | 6 ++--- drivers/clk/qcom/clock-qcs8300.c | 4 +-- drivers/clk/qcom/clock-sa8775p.c | 4 +-- drivers/clk/qcom/clock-sc7280.c | 8 +++--- drivers/clk/qcom/clock-sdm845.c | 42 +++++++++++++++--------------- drivers/clk/qcom/clock-sm6125.c | 8 +++--- drivers/clk/qcom/clock-sm6350.c | 4 +-- drivers/clk/qcom/clock-sm8150.c | 14 +++++----- drivers/clk/qcom/clock-sm8550.c | 16 ++++++------ drivers/clk/qcom/clock-sm8650.c | 16 ++++++------ drivers/clk/qcom/clock-x1e80100.c | 54 +++++++++++++++++++-------------------- 11 files changed, 88 insertions(+), 88 deletions(-) diff --git a/drivers/clk/qcom/clock-milos.c b/drivers/clk/qcom/clock-milos.c index 54103adc114..bb2cb19aeb2 100644 --- a/drivers/clk/qcom/clock-milos.c +++ b/drivers/clk/qcom/clock-milos.c @@ -130,9 +130,9 @@ static const struct qcom_reset_map milos_gcc_resets[] = { }; static const struct qcom_power_map milos_gdscs[] = { - [UFS_PHY_GDSC] = { 0x77004 }, - [UFS_MEM_PHY_GDSC] = { 0x9e000 }, - [USB30_PRIM_GDSC] = { 0x39004 }, + [UFS_PHY_GDSC] = { .reg = 0x77004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [UFS_MEM_PHY_GDSC] = { .reg = 0x9e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [USB30_PRIM_GDSC] = { .reg = 0x39004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, }; static struct msm_clk_data milos_gcc_data = { diff --git a/drivers/clk/qcom/clock-qcs8300.c b/drivers/clk/qcom/clock-qcs8300.c index cd8aecdf788..9cf48fc9d6d 100644 --- a/drivers/clk/qcom/clock-qcs8300.c +++ b/drivers/clk/qcom/clock-qcs8300.c @@ -112,8 +112,8 @@ static const struct qcom_reset_map qcs8300_gcc_resets[] = { }; static const struct qcom_power_map qcs8300_gdscs[] = { - [GCC_UFS_PHY_GDSC] = { 0x83004 }, - [GCC_USB30_PRIM_GDSC] = { 0x1B004 }, + [GCC_UFS_PHY_GDSC] = { .reg = 0x83004, .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR }, + [GCC_USB30_PRIM_GDSC] = { .reg = 0x1B004, .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR }, }; static struct msm_clk_data qcs8300_gcc_data = { diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c index 7eec4aeae48..3a014c63c0c 100644 --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -243,8 +243,8 @@ static const struct qcom_reset_map sa8775p_gcc_resets[] = { }; static const struct qcom_power_map sa8775p_gdscs[] = { - [UFS_PHY_GDSC] = { 0x83004 }, - [USB30_PRIM_GDSC] = { 0x1B004 }, + [UFS_PHY_GDSC] = { .reg = 0x83004, .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR }, + [USB30_PRIM_GDSC] = { .reg = 0x1B004, .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR }, }; static struct msm_clk_data sa8775_gcc_data = { diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 91e3fcc27cb..9cf665552ba 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -282,10 +282,10 @@ static const struct qcom_reset_map sc7280_gcc_resets[] = { }; static const struct qcom_power_map sc7280_gdscs[] = { - [GCC_UFS_PHY_GDSC] = { 0x77004 }, - [GCC_USB30_PRIM_GDSC] = { 0xf004 }, - [GCC_USB30_SEC_GDSC] = { 0x9e004 }, - [GCC_PCIE_1_GDSC] = { 0x8d004 }, + [GCC_UFS_PHY_GDSC] = { .reg = 0x77004, .flags = VOTABLE }, + [GCC_USB30_PRIM_GDSC] = { .reg = 0xf004, .flags = VOTABLE }, + [GCC_USB30_SEC_GDSC] = { .reg = 0x9e004, .flags = VOTABLE }, + [GCC_PCIE_1_GDSC] = { .reg = 0x8d004, .flags = VOTABLE }, }; static const phys_addr_t sc7280_rcg_addrs[] = { diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index c9a057cf6f9..df37f4bd33f 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -288,30 +288,30 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { }; static const struct qcom_power_map sdm670_gdscs[] = { - [UFS_PHY_GDSC] = { 0x77004 }, - [USB30_PRIM_GDSC] = { 0xf004 }, - [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, - [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, - [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, + [UFS_PHY_GDSC] = { .reg = 0x77004, .flags = POLL_CFG_GDSCR }, + [USB30_PRIM_GDSC] = { .reg = 0xf004, .flags = POLL_CFG_GDSCR }, + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { .reg = 0x7d030, .flags = VOTABLE }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { .reg = 0x7d034, .flags = VOTABLE }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { .reg = 0x7d038, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { .reg = 0x7d040, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { .reg = 0x7d048, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { .reg = 0x7d044, .flags = VOTABLE }, }; static const struct qcom_power_map sdm845_gdscs[] = { - [PCIE_0_GDSC] = { 0x6b004 }, - [PCIE_1_GDSC] = { 0x8d004 }, - [UFS_CARD_GDSC] = { 0x75004 }, - [UFS_PHY_GDSC] = { 0x77004 }, - [USB30_PRIM_GDSC] = { 0xf004 }, - [USB30_SEC_GDSC] = { 0x10004 }, - [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, - [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, - [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, - [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, + [PCIE_0_GDSC] = { .reg = 0x6b004, .flags = POLL_CFG_GDSCR }, + [PCIE_1_GDSC] = { .reg = 0x8d004, .flags = POLL_CFG_GDSCR }, + [UFS_CARD_GDSC] = {.reg = 0x75004, .flags = POLL_CFG_GDSCR }, + [UFS_PHY_GDSC] = { .reg = 0x77004, .flags = POLL_CFG_GDSCR }, + [USB30_PRIM_GDSC] = { .reg = 0xf004, .flags = POLL_CFG_GDSCR }, + [USB30_SEC_GDSC] = { .reg = 0x10004, .flags = POLL_CFG_GDSCR }, + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { .reg = 0x7d030, .flags = VOTABLE }, + [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { .reg = 0x7d03c, .flags = VOTABLE }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { .reg = 0x7d034, .flags = VOTABLE }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { .reg = 0x7d038, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { .reg = 0x7d040, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { .reg = 0x7d048, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { .reg = 0x7d044, .flags = VOTABLE }, }; static const phys_addr_t sdm845_gpll_addrs[] = { diff --git a/drivers/clk/qcom/clock-sm6125.c b/drivers/clk/qcom/clock-sm6125.c index 1fd72d55e88..6189c5070e9 100644 --- a/drivers/clk/qcom/clock-sm6125.c +++ b/drivers/clk/qcom/clock-sm6125.c @@ -176,10 +176,10 @@ static const struct qcom_power_map sm6125_gdscs[] = { [CAMSS_VFE1_GDSC] = { 0x5403c }, [CAMSS_TOP_GDSC] = { 0x5607c }, [CAM_CPP_GDSC] = { 0x560bc }, - [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = { 0x7d060 }, - [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = { 0x80074 }, - [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = { 0x80084 }, - [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = { 0x80094 }, + [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = { .reg = 0x7d060, .flags = VOTABLE }, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = { .reg = 0x80074, .flags = VOTABLE }, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = { .reg = 0x80084, .flags = VOTABLE }, + [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = { .reg = 0x80094, .flags = VOTABLE }, }; static const phys_addr_t sm6125_gpll_addrs[] = { diff --git a/drivers/clk/qcom/clock-sm6350.c b/drivers/clk/qcom/clock-sm6350.c index ee6653848c7..aa92359fa49 100644 --- a/drivers/clk/qcom/clock-sm6350.c +++ b/drivers/clk/qcom/clock-sm6350.c @@ -160,8 +160,8 @@ static const struct qcom_reset_map sm6350_gcc_resets[] = { static const struct qcom_power_map sm6350_gdscs[] = { [USB30_PRIM_GDSC] = { 0x1a004 }, [UFS_PHY_GDSC] = { 0x3a004 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0xb7040 }, - [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0xb7044 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { .reg = 0xb7040, .flags = VOTABLE }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { .reg = 0xb7044, .flags = VOTABLE }, }; static struct msm_clk_data sm6350_gcc_data = { diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c index 7dd0d56eb43..5667396ab01 100644 --- a/drivers/clk/qcom/clock-sm8150.c +++ b/drivers/clk/qcom/clock-sm8150.c @@ -279,13 +279,13 @@ static const struct qcom_reset_map sm8150_gcc_resets[] = { }; static const struct qcom_power_map sm8150_gcc_power_domains[] = { - [EMAC_GDSC] = { 0x6004 }, - [PCIE_0_GDSC] = { 0x6b004 }, - [PCIE_1_GDSC] = { 0x8d004 }, - [UFS_CARD_GDSC] = { 0x75004 }, - [UFS_PHY_GDSC] = { 0x77004 }, - [USB30_PRIM_GDSC] = { 0xf004 }, - [USB30_SEC_GDSC] = { 0x10004 }, + [EMAC_GDSC] = { .reg = 0x6004, .flags = POLL_CFG_GDSCR }, + [PCIE_0_GDSC] = { .reg = 0x6b004, .flags = POLL_CFG_GDSCR }, + [PCIE_1_GDSC] = { .reg = 0x8d004, .flags = POLL_CFG_GDSCR }, + [UFS_CARD_GDSC] = { .reg = 0x75004, .flags = POLL_CFG_GDSCR }, + [UFS_PHY_GDSC] = { .reg = 0x77004, .flags = POLL_CFG_GDSCR }, + [USB30_PRIM_GDSC] = { .reg = 0xf004, .flags = POLL_CFG_GDSCR }, + [USB30_SEC_GDSC] = { .reg = 0x10004, .flags = POLL_CFG_GDSCR }, }; static struct msm_clk_data sm8150_clk_data = { diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c index 7c06489b9c4..cf96f1c631f 100644 --- a/drivers/clk/qcom/clock-sm8550.c +++ b/drivers/clk/qcom/clock-sm8550.c @@ -263,14 +263,14 @@ static const struct qcom_reset_map sm8550_gcc_resets[] = { }; static const struct qcom_power_map sm8550_gdscs[] = { - [PCIE_0_GDSC] = { 0x6b004 }, - [PCIE_0_PHY_GDSC] = { 0x6c000 }, - [PCIE_1_GDSC] = { 0x8d004 }, - [PCIE_1_PHY_GDSC] = { 0x8e000 }, - [UFS_PHY_GDSC] = { 0x77004 }, - [UFS_MEM_PHY_GDSC] = { 0x9e000 }, - [USB30_PRIM_GDSC] = { 0x39004 }, - [USB3_PHY_GDSC] = { 0x50018 }, + [PCIE_0_GDSC] = { .reg = 0x6b004, .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [PCIE_0_PHY_GDSC] = { .reg = 0x6c000, .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [PCIE_1_GDSC] = { .reg = 0x8d004, .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [PCIE_1_PHY_GDSC] = { .reg = 0x8e000, .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [UFS_PHY_GDSC] = { .reg = 0x77004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [UFS_MEM_PHY_GDSC] = { .reg = 0x9e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [USB30_PRIM_GDSC] = { .reg = 0x39004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [USB3_PHY_GDSC] = { .reg = 0x50018, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, }; static struct msm_clk_data sm8550_gcc_data = { diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 7c49e99c005..dfe7bc6ce90 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -261,14 +261,14 @@ static const struct qcom_reset_map sm8650_gcc_resets[] = { }; static const struct qcom_power_map sm8650_gdscs[] = { - [PCIE_0_GDSC] = { 0x6b004 }, - [PCIE_0_PHY_GDSC] = { 0x6c000 }, - [PCIE_1_GDSC] = { 0x8d004 }, - [PCIE_1_PHY_GDSC] = { 0x8e000 }, - [UFS_PHY_GDSC] = { 0x77004 }, - [UFS_MEM_PHY_GDSC] = { 0x9e000 }, - [USB30_PRIM_GDSC] = { 0x39004 }, - [USB3_PHY_GDSC] = { 0x50018 }, + [PCIE_0_GDSC] = { .reg = 0x6b004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [PCIE_0_PHY_GDSC] = { .reg = 0x6c000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [PCIE_1_GDSC] = { .reg = 0x8d004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [PCIE_1_PHY_GDSC] = { .reg = 0x8e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [UFS_PHY_GDSC] = { .reg = 0x77004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [UFS_MEM_PHY_GDSC] = { .reg = 0x9e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [USB30_PRIM_GDSC] = { .reg = 0x39004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [USB3_PHY_GDSC] = { .reg = 0x50018, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, }; static struct msm_clk_data sm8650_gcc_data = { diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c index 542d6248d65..bed3b2b8f2c 100644 --- a/drivers/clk/qcom/clock-x1e80100.c +++ b/drivers/clk/qcom/clock-x1e80100.c @@ -269,33 +269,33 @@ static const struct qcom_reset_map x1e80100_gcc_resets[] = { }; static const struct qcom_power_map x1e80100_gdscs[] = { - [GCC_PCIE_0_TUNNEL_GDSC] = { 0xa0004 }, - [GCC_PCIE_1_TUNNEL_GDSC] = { 0x2c004 }, - [GCC_PCIE_2_TUNNEL_GDSC] = { 0x13004 }, - [GCC_PCIE_3_GDSC] = { 0x58004 }, - [GCC_PCIE_3_PHY_GDSC] = { 0x3e000 }, - [GCC_PCIE_4_GDSC] = { 0x6b004 }, - [GCC_PCIE_4_PHY_GDSC] = { 0x6c000 }, - [GCC_PCIE_5_GDSC] = { 0x2f004 }, - [GCC_PCIE_5_PHY_GDSC] = { 0x30000 }, - [GCC_PCIE_6_PHY_GDSC] = { 0x8e000 }, - [GCC_PCIE_6A_GDSC] = { 0x31004 }, - [GCC_PCIE_6B_GDSC] = { 0x8d004 }, - [GCC_UFS_MEM_PHY_GDSC] = { 0x9e000 }, - [GCC_UFS_PHY_GDSC] = { 0x77004 }, - [GCC_USB20_PRIM_GDSC] = { 0x29004 }, - [GCC_USB30_MP_GDSC] = { 0x17004 }, - [GCC_USB30_PRIM_GDSC] = { 0x39004 }, - [GCC_USB30_SEC_GDSC] = { 0xa1004 }, - [GCC_USB30_TERT_GDSC] = { 0xa2004 }, - [GCC_USB3_MP_SS0_PHY_GDSC] = { 0x1900c }, - [GCC_USB3_MP_SS1_PHY_GDSC] = { 0x5400c }, - [GCC_USB4_0_GDSC] = { 0x9f004 }, - [GCC_USB4_1_GDSC] = { 0x2b004 }, - [GCC_USB4_2_GDSC] = { 0x11004 }, - [GCC_USB_0_PHY_GDSC] = { 0x50024 }, - [GCC_USB_1_PHY_GDSC] = { 0x2a024 }, - [GCC_USB_2_PHY_GDSC] = { 0xa3024 }, + [GCC_PCIE_0_TUNNEL_GDSC] = { .reg = 0xa0004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_1_TUNNEL_GDSC] = { .reg = 0x2c004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_2_TUNNEL_GDSC] = { .reg = 0x13004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_3_GDSC] = { .reg = 0x58004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_3_PHY_GDSC] = { .reg = 0x3e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_4_GDSC] = { .reg = 0x6b004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_4_PHY_GDSC] = { .reg = 0x6c000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_5_GDSC] = { .reg = 0x2f004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_5_PHY_GDSC] = { .reg = 0x30000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_6_PHY_GDSC] = { .reg = 0x8e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_6A_GDSC] = { .reg = 0x31004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_PCIE_6B_GDSC] = { .reg = 0x8d004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE }, + [GCC_UFS_MEM_PHY_GDSC] = { .reg = 0x9e000, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_UFS_PHY_GDSC] = { .reg = 0x77004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB20_PRIM_GDSC] = { .reg = 0x29004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB30_MP_GDSC] = { .reg = 0x17004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB30_PRIM_GDSC] = { .reg = 0x39004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB30_SEC_GDSC] = { .reg = 0xa1004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB30_TERT_GDSC] = { .reg = 0xa2004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB3_MP_SS0_PHY_GDSC] = { .reg = 0x1900c, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB3_MP_SS1_PHY_GDSC] = { .reg = 0x5400c, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB4_0_GDSC] = { .reg = 0x9f004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB4_1_GDSC] = { .reg = 0x2b004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB4_2_GDSC] = { .reg = 0x11004, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB_0_PHY_GDSC] = { .reg = 0x50024, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB_1_PHY_GDSC] = { .reg = 0x2a024, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, + [GCC_USB_2_PHY_GDSC] = { .reg = 0xa3024, .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE }, }; static struct msm_clk_data x1e80100_gcc_data = { -- 2.55.0
