Add clock tree type flags to the mt8195 clock tree structures. These will be used later for parent lookup.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt8195.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c index 37cceb5f32b..3afae4d725c 100644 --- a/drivers/clk/mediatek/clk-mt8195.c +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -101,6 +101,7 @@ static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = { .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .num_plls = ARRAY_SIZE(apmixed_plls), + .type = MTK_CLK_TREE_APMIXED, }; #define FIXED_CLK0(_id, _rate) \ @@ -1423,6 +1424,7 @@ static const struct mtk_clk_tree mt8195_topckgen_clk_tree = { .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), .num_gates = ARRAY_SIZE(top_cg_clks), + .type = MTK_CLK_TREE_TOPCKGEN, }; static const struct mtk_gate_regs infra_ao0_cg_regs = { @@ -1635,6 +1637,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = { .name = "mt8195-apmixedsys", .id = UCLASS_CLK, .of_match = mt8195_apmixed, + .bind = mtk_common_clk_parent_bind, .probe = mt8195_apmixedsys_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_apmixedsys_ops, @@ -1645,6 +1648,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .name = "mt8195-topckgen", .id = UCLASS_CLK, .of_match = mt8195_topckgen_compat, + .bind = mtk_common_clk_parent_bind, .probe = mt8195_topckgen_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_topckgen_ops, -- 2.43.0
