Signed-off-by: Reinhard Meyer <u-b...@emk-elektronik.de>
---
arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c | 88 +++++-----
arch/arm/include/asm/arch-at91/at91cap9.h | 214 +++++++++++-----------
arch/arm/include/asm/arch-at91/at91cap9_matrix.h | 147 +++++-----------
3 files changed, 191 insertions(+), 258 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
index 2d878fd..2a0d7a3 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
@@ -27,77 +27,73 @@
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
void at91_serial0_hw_init(void)
{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */
- writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
+ at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* RXD0 */
+ writel(1 << ATMEL_ID_USART0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */
- writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
+ at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */
+ writel(1 << ATMEL_ID_USART1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */
- writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
+ at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */
+ writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}
-void at91_serial3_hw_init(void)
+void at91_seriald_hw_init(void)
{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
- writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
- at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
- at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
- at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3 /* DBGU */
- at91_serial3_hw_init();
-#endif
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
-#ifdef CONFIG_HAS_DATAFLASH
+#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
+ at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
+ at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
+ at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
/* Enable clock */
- writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
+ writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
@@ -127,14 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */
/* Enable clock */
- writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
+ writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
@@ -194,12 +190,12 @@ void at91_macb_hw_init(void)
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */
at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */
/* Enable clock */
- writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
+ writel(1 << ATMEL_ID_CAN, &pmc->pcer);
}
#endif
diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h
b/arch/arm/include/asm/arch-at91/at91cap9.h
index 5af6fdc..a41f755 100644
--- a/arch/arm/include/asm/arch-at91/at91cap9.h
+++ b/arch/arm/include/asm/arch-at91/at91cap9.h
@@ -18,133 +18,133 @@
#define AT91CAP9_H
/*
- * Peripheral identifiers/interrupts.
+ * defines to be used in other places
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ)
*/
-#define AT91_ID_SYS 1 /* System Peripherals */
-#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D
*/
-#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
-#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
-#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
-#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
-#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
-#define AT91CAP9_ID_US0 8 /* USART 0 */
-#define AT91CAP9_ID_US1 9 /* USART 1 */
-#define AT91CAP9_ID_US2 10 /* USART 2 */
-#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
-#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
-#define AT91CAP9_ID_CAN 13 /* CAN */
-#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
-#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
-#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
-#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
-#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
-#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
-#define AT91CAP9_ID_EMAC 22 /* Ethernet */
-#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple
DES */
-#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter
*/
-#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
-#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
-#define AT91CAP9_ID_DMA 27 /* DMA Controller */
-#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
-#define AT91CAP9_ID_UHP 29 /* USB Host Port */
-#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0)
*/
-#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1)
*/
-
-#define AT91_PIO_BASE 0xfffff200
-#define AT91_PMC_BASE 0xfffffc00
-#define AT91_RSTC_BASE 0xfffffd00
-#define AT91_PIT_BASE 0xfffffd30
-
-#ifdef CONFIG_AT91_LEGACY
+#define CONFIG_ARM926EJS /* ARM926EJS Core */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
- * User Peripheral physical base addresses.
+ * Peripheral identifiers/interrupts.
*/
-#define AT91CAP9_BASE_UDPHS 0xfff78000
-#define AT91CAP9_BASE_TCB0 0xfff7c000
-#define AT91CAP9_BASE_TC0 0xfff7c000
-#define AT91CAP9_BASE_TC1 0xfff7c040
-#define AT91CAP9_BASE_TC2 0xfff7c080
-#define AT91CAP9_BASE_MCI0 0xfff80000
-#define AT91CAP9_BASE_MCI1 0xfff84000
-#define AT91CAP9_BASE_TWI 0xfff88000
-#define AT91CAP9_BASE_US0 0xfff8c000
-#define AT91CAP9_BASE_US1 0xfff90000
-#define AT91CAP9_BASE_US2 0xfff94000
-#define AT91CAP9_BASE_SSC0 0xfff98000
-#define AT91CAP9_BASE_SSC1 0xfff9c000
-#define AT91CAP9_BASE_AC97C 0xfffa0000
-#define AT91CAP9_BASE_SPI0 0xfffa4000
-#define AT91CAP9_BASE_SPI1 0xfffa8000
-#define AT91CAP9_BASE_CAN 0xfffac000
-#define AT91CAP9_BASE_PWMC 0xfffb8000
-#define AT91CAP9_BASE_EMAC 0xfffbc000
-#define AT91CAP9_BASE_ADC 0xfffc0000
-#define AT91CAP9_BASE_ISI 0xfffc4000
-#define AT91_BASE_SYS 0xffffe200
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Peripherals */
+#define ATMEL_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
+#define ATMEL_ID_MPB0 3 /* MP Block Peripheral 0 */
+#define ATMEL_ID_MPB1 4 /* MP Block Peripheral 1 */
+#define ATMEL_ID_MPB2 5 /* MP Block Peripheral 2 */
+#define ATMEL_ID_MPB3 6 /* MP Block Peripheral 3 */
+#define ATMEL_ID_MPB4 7 /* MP Block Peripheral 4 */
+#define ATMEL_ID_USART0 8 /* USART 0 */
+#define ATMEL_ID_USART1 9 /* USART 1 */
+#define ATMEL_ID_USART2 10 /* USART 2 */
+#define ATMEL_ID_MCI0 11 /* Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1 12 /* Multimedia Card Interface 1 */
+#define ATMEL_ID_CAN 13 /* CAN */
+#define ATMEL_ID_TWI 14 /* Two-Wire Interface */
+#define ATMEL_ID_SPI0 15 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 16 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SSC0 17 /* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1 18 /* Serial Synchronous Controller 1 */
+#define ATMEL_ID_AC97C 19 /* AC97 Controller */
+#define ATMEL_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
+#define ATMEL_ID_PWMC 21 /* Pulse Width Modulation Controller */
+#define ATMEL_ID_EMAC 22 /* Ethernet */
+#define ATMEL_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
+#define ATMEL_ID_ADC 24 /* Analog-to-Digital Converter */
+#define ATMEL_ID_ISI 25 /* Image Sensor Interface */
+#define ATMEL_ID_LCDC 26 /* LCD Controller */
+#define ATMEL_ID_DMA 27 /* DMA Controller */
+#define ATMEL_ID_UDPHS 28 /* USB High Speed Device Port */
+#define ATMEL_ID_UHP 29 /* USB Host Port */
+#define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
+#define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * User Peripheral physical base addresses.
*/
-#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
-#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
-#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
-#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
-#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS)
-
-#define AT91_USART0 AT91CAP9_BASE_US0
-#define AT91_USART1 AT91CAP9_BASE_US1
-#define AT91_USART2 AT91CAP9_BASE_US2
+#define ATMEL_BASE_UDPHS 0xfff78000
+#define ATMEL_BASE_TCB0 0xfff7c000
+#define ATMEL_BASE_TC0 0xfff7c000
+#define ATMEL_BASE_TC1 0xfff7c040
+#define ATMEL_BASE_TC2 0xfff7c080
+#define ATMEL_BASE_MCI0 0xfff80000
+#define ATMEL_BASE_MCI1 0xfff84000
+#define ATMEL_BASE_TWI 0xfff88000
+#define ATMEL_BASE_USART0 0xfff8c000
+#define ATMEL_BASE_USART1 0xfff90000
+#define ATMEL_BASE_USART2 0xfff94000
+#define ATMEL_BASE_SSC0 0xfff98000
+#define ATMEL_BASE_SSC1 0xfff9c000
+#define ATMEL_BASE_AC97C 0xfffa0000
+#define ATMEL_BASE_SPI0 0xfffa4000
+#define ATMEL_BASE_SPI1 0xfffa8000
+#define ATMEL_BASE_CAN 0xfffac000
+#define ATMEL_BASE_PWMC 0xfffb8000
+#define ATMEL_BASE_EMAC 0xfffbc000
+#define ATMEL_BASE_ADC 0xfffc0000
+#define ATMEL_BASE_ISI 0xfffc4000
/*
- * SCKCR flags
+ * System Peripherals physical base addresses.
*/
-#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
-#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
-#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator
Bypass */
-#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
-#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3)
-#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)
+#define ATMEL_BASE_ECC 0xffffe200
+#define ATMEL_BASE_BCRAMC 0xffffe400
+#define ATMEL_BASE_DDRSDRC 0xffffe600
+#define ATMEL_BASE_SMC 0xffffe800
+#define ATMEL_BASE_MATRIX 0xffffea00
+#define ATMEL_BASE_CCFG 0xffffeb10
+#define ATMEL_BASE_DMA 0xffffec00
+#define ATMEL_BASE_DBGU 0xffffee00
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_PIOA 0xfffff200
+#define ATMEL_BASE_PIOB 0xfffff400
+#define ATMEL_BASE_PIOC 0xfffff600
+#define ATMEL_BASE_PIOD 0xfffff800
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffd00
+#define ATMEL_BASE_SHDWC 0xfffffd10
+#define ATMEL_BASE_RTT 0xfffffd20
+#define ATMEL_BASE_PIT 0xfffffd30
+#define ATMEL_BASE_WDT 0xfffffd40
+#define ATMEL_BASE_SCKCR 0xfffffd50
+#define ATMEL_BASE_GPBR_REVB 0xfffffd50
+#define ATMEL_BASE_GPBR_REVC 0xfffffd60
-#endif /* CONFIG_AT91_LEGACY */
/*
* Internal Memory.
*/
-#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
-#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
+#define ATMEL_BASE_SRAM 0x00100000 /* Internal SRAM */
-#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
-#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
+#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */
-#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
-#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
-#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
+#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */
+#define ATMEL_BASE_UHPHS 0x00600000 /* USB High Speed Device */
+#define ATMEL_BASE_UHP 0x00700000 /* USB Host controller */
-#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000
+#define ATMEL_BASE_CS1 0x20000000
+#define ATMEL_BASE_CS2 0x30000000
+#define ATMEL_BASE_CS3 0x40000000
+#define ATMEL_BASE_CS4 0x50000000
+#define ATMEL_BASE_CS5 0x60000000
+#define ATMEL_BASE_CS6 0x70000000
+#define ATMEL_BASE_CS7 0x80000000
+
+#define CONFIG_DRAM_BASE ATMEL_BASE_CS6
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 4 /* this SoCs has 4 PIO
*/
+#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
/*
* Cpu Name
*/
-#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9"
+#define ATMEL_CPU_NAME "AT91CAP9"
#endif
diff --git a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
index 22b7e9b..3088287 100644
--- a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
@@ -17,116 +17,53 @@
#ifndef AT91CAP9_MATRIX_H
#define AT91CAP9_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration
Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration
Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration
Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration
Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration
Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration
Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration
Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration
Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration
Register 8 */
-#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration
Register 9 */
-#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration
Register 10 */
-#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration
Register 11 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined
Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#ifndef __ASSEMBLY__
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration
Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration
Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration
Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration
Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration
Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration
Register 5 */
-#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration
Register 6 */
-#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration
Register 7 */
-#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration
Register 8 */
-#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration
Register 9 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /*
Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /*
Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /*
Fixed Index of Default Master */
-#define AT91_MATRIX_ARBT (3 << 24) /*
Arbitration Type */
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+/*
+ * This struct defines access to the matrix' maximum of
+ * 16 masters and 16 slaves.
+ * Note: not all masters/slaves are available
+ */
+struct at91_matrix {
+ u32 mcfg[16]; /* Master Configuration Registers */
+ u32 scfg[16]; /* Slave Configuration Registers */
+ u32 pras[16][2]; /* Priority Assignment Slave Registers */
+ u32 mrcr; /* Master Remap Control Register */
+ u32 filler[0x06];
+ u32 ebicsa; /* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A
for Slave 0 */
-#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B
for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A
for Slave 1 */
-#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B
for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A
for Slave 2 */
-#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B
for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A
for Slave 3 */
-#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B
for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A
for Slave 4 */
-#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B
for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A
for Slave 5 */
-#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B
for Slave 5 */
-#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A
for Slave 6 */
-#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B
for Slave 6 */
-#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A
for Slave 7 */
-#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B
for Slave 7 */
-#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A
for Slave 8 */
-#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B
for Slave 8 */
-#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A
for Slave 9 */
-#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B
for Slave 9 */
-#define AT91_MATRIX_M0PR (3 << 0) /*
Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /*
Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /*
Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /*
Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /*
Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /*
Master 5 Priority */
-#define AT91_MATRIX_M6PR (3 << 24) /*
Master 6 Priority */
-#define AT91_MATRIX_M7PR (3 << 28) /*
Master 7 Priority */
-#define AT91_MATRIX_M8PR (3 << 0) /*
Master 8 Priority (in Register B) */
-#define AT91_MATRIX_M9PR (3 << 4) /*
Master 9 Priority (in Register B) */
-#define AT91_MATRIX_M10PR (3 << 8) /*
Master 10 Priority (in Register B) */
-#define AT91_MATRIX_M11PR (3 << 12) /*
Master 11 Priority (in Register B) */
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control
Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /*
Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /*
Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_RCB9 (1 << 9)
-#define AT91_MATRIX_RCB10 (1 << 10)
-#define AT91_MATRIX_RCB11 (1 << 11)
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0
Special Function Register */
-#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1
Special Function Register */
+#define AT91_MATRIX_M0PR_SHIFT 0
+#define AT91_MATRIX_M1PR_SHIFT 4
+#define AT91_MATRIX_M2PR_SHIFT 8
+#define AT91_MATRIX_M3PR_SHIFT 12
+#define AT91_MATRIX_M4PR_SHIFT 16
+#define AT91_MATRIX_M5PR_SHIFT 20
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select
Assignment Register */
-#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip
Select 1 Assignment */
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip
Select 3 Assignment */
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip
Select 4 Assignment */
-#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip
Select 5 Assignment */
-#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data
Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data
Qualifier Strobe Pull-Down Configuration */
-#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /*
Memory voltage selection */
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 <<
16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 <<
16)
+#define AT91_MATRIX_RCB0 (1 << 0)
+#define AT91_MATRIX_RCB1 (1 << 1)
-#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2
Special Function Register */
-#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3
Special Function Register */
-#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special
Function Register */
+#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91_MATRIX_DBPUC (1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
#endif
--
1.7.4.1
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