From: Dinesh Maniyam <[email protected]> drivers/mtd/nand/raw/cadence_spl.c, selected by SPL_NAND_CADENCE, is a thin generic SPL helper on top of the nand_chip framework rather than a Cadence-specific driver: nand_is_bad_block() uses CONFIG_SYS_NAND_BLOCK_SIZE to compute block offsets for chip->block_bad(), and nand_read_page() calls nand_read(). It works with any full NAND driver that registers a chip.
SYS_NAND_BLOCK_SIZE currently excludes NAND_DENALI_DT boards on the (correct) assumption that the full Denali driver auto-detects geometry via ONFI at runtime. This precludes boards like SoCFPGA Arria 10 SoCDK that pair NAND_DENALI_DT (full U-Boot) with SPL_NAND_CADENCE (SPL loader) and need the eraseblock size statically for the SPL helper. Allow the symbol to also be visible when SPL_NAND_CADENCE is set. Pure Denali boards (uniphier) keep the existing behaviour and their .config is unchanged. Signed-off-by: Dinesh Maniyam <[email protected]> --- drivers/mtd/nand/raw/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 261b9a51dd7..4850e0b2554 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -662,8 +662,9 @@ config SYS_NAND_BLOCK_SIZE hex "NAND chip eraseblock size" depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT || \ MVEBU_SPL_BOOT_DEVICE_NAND - depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \ + depends on !NAND_MXS && !NAND_LPC32XX_MLC && \ !NAND_FSL_IFC && !NAND_MT7621 + depends on !NAND_DENALI_DT || SPL_NAND_CADENCE help Number of data bytes in one eraseblock for the NAND chip on the board. This is the multiple of NAND_PAGE_SIZE and the number of -- 2.43.7
