Hi Jonas, Simon, Thanks for the review -- much appreciated. A short status and plan rather than a new posting.
Following the feedback, the work-in-progress series now: - drops OF_PLATDATA and the clock driver from TPL (DRAM init uses the CRU registers directly), keeping TPL minimal; - drops the DT / syscon additions (no dt-bindings submitted yet); - restores the original Rockchip copyright notices; - stays TPL-only, no DVFS or other complex scenarios. Still to do before the next revision: Simon's obj-$(CONFIG_$(PHASE_)SYSRESET_PSCI) suggestion, and the substantive part -- real timing values (the tables are still TRM reset defaults) plus hardware bring-up. That last piece is the real gate; I would rather not re-post a series that does not train DRAM yet. Per your note, I will hold the next RK3576 revision until Pavel's RK3568 series settles, to avoid two parallel reviews. I am following that thread and will rebase onto the agreed approach (including the TPL size work) before re-posting. WIP and notes live at https://github.com/OpenHorse/rk3576-dram-init for anyone following along. Thanks again, Johan
