Hi Tien Fong,
On 7/5/2026 4:37 pm, Chee, Tien Fong wrote:
Hi Alif,
On 28/4/2026 11:48 am, [email protected] wrote:
From: Alif Zakuan Yuslaimi <[email protected]>
Migrate the legacy Stratix10 platform to use the upstream Linux device
tree
configuration. This helps reduce maintenance overhead and aligns U-Boot
with the Linux kernel's DTS hierarchy and naming conventions.
This change improves consistency between U-Boot and Linux by removing
custom/legacy DTS handling and instead relying on the standardized
definitions provided by the upstream Linux DTS.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
---
Please add the change log for each version.
Noted, I will add change log for related patches in v3.
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 158 +++++++
arch/arm/dts/socfpga_stratix10.dtsi | 430 ------------------
.../dts/socfpga_stratix10_socdk-u-boot.dtsi | 143 +++++-
arch/arm/dts/socfpga_stratix10_socdk.dts | 143 ------
configs/socfpga_stratix10_defconfig | 3 +-
6 files changed, 286 insertions(+), 594 deletions(-)
delete mode 100644 arch/arm/dts/socfpga_stratix10.dtsi
delete mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bff341d6118..2832123218f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -460,8 +460,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_vining_fpga.dtb \
socfpga_cyclone5_ac501soc.dtb \
socfpga_cyclone5_ac550soc.dtb \
- socfpga_n5x_socdk.dtb \
- socfpga_stratix10_socdk.dtb
+ socfpga_n5x_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/
dts/socfpga_stratix10-u-boot.dtsi
index 3e3a3780469..a3b4c0564f9 100644
--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
@@ -3,6 +3,164 @@
* U-Boot additions
*
* Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2026 Altera Corporation <www.altera.com>
*/
#include "socfpga_soc64_fit-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = &qspi;
+ i2c0 = &i2c1;
+ freeze_br0 = &freeze_controller;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ #address-cells = <2>;
+ #size-cells = <2>;
make dtbs_check (Linux dt-validate) will flag it as a schema violation
since memory nodes must not define #address-cells / #size-cells because
no child node according to the dt spec.
Remove both properties from the memory@0
[...]
Removing these properties will result in boot failure in SPL during DDR
init.
fdtdec_decode_ram_size() in lib/fdtdec.c applied #cells to the wrong DT
node, triggering libfdt’s default #size-cells = 1, which misparses reg
encoded for #size-cells = <2> which is the way to describe 64-bit
physical addresses and sizes ≥ 4 GiB for Stratix10.
Refer commit - 90c08fa038451d6d7b7d8711bfd829b61d64c490
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/
arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index ef0df769762..da19943ec3b 100644
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -3,47 +3,154 @@
* U-Boot additions
*
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
+ * Copyright (C) 2026 Altera Corporation <www.altera.com>
*/
#include "socfpga_stratix10-u-boot.dtsi"
/{
- aliases {
- spi0 = &qspi;
- freeze_br0 = &freeze_controller;
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = &mmc,&flash0,&nand;
};
- soc {
- freeze_controller: freeze_controller@f9000450 {
- compatible = "altr,freeze-bridge-controller";
- reg = <0xf9000450 0x00000010>;
- status = "disabled";
+ memory@0 {
+ /* 4GB */
+ reg = <0 0x00000000 0 0x80000000>,
+ <1 0x80000000 0 0x80000000>;
+ };
+};
+
+&qspi {
+ status = "okay";
+};
+
+&gmac0 {
+ mdio0 {
+ ethernet_phy0: ethernet-phy@0 {
+ reg = <4>;
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <900>; /* 0ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
};
};
};
-&clkmgr {
+&mmc {
+ drvsel = <3>;
+ smplsel = <2>;
bootph-all;
};
&qspi {
- status = "okay";
- bootph-all;
+ /delete-property/ clocks;
};
&flash0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <100000000>;
+ reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
bootph-all;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ /delete-property/ cdns,read-delay;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x04200000>;
+ };
+
+ root: partition@4200000 {
+ label = "root";
+ reg = <0x04200000 0x0BE00000>;
+ };
+ };
};
-&sysmgr {
- bootph-all;
+&fdt_0_blob {
+ filename = "dts/upstream/src/arm64/altera/
socfpga_stratix10_socdk.dtb";
};
-&watchdog0 {
- status = "okay";
- bootph-all;
+&images {
+ fdt-1 {
+ description = "socfpga_socdk_nand";
+ type = "flat_dt";
+ compression = "none";
+ fdt_1_blob: blob-ext {
+ filename = "dts/upstream/src/arm64/altera/
socfpga_stratix10_socdk_nand.dtb";
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
+ fdt-2 {
+ description = "socfpga_socdk_emmc";
+ type = "flat_dt";
+ compression = "none";
+ fdt_2_blob: blob-ext {
+ filename = "dts/upstream/src/arm64/altera/
socfpga_stratix10_socdk_emmc.dtb";
This file is absent. Binman references dts/upstream/src/arm64/altera/
socfpga_stratix10_socdk_emmc.dtb.
If those source DTS files do not exist in the upstream tree, binman
fails with a file-not-found error at image build time
Best regards,
Tien Fong
