Change CLK_TOP_CLK26M rate from 260_000_000 to 26_000_000. As the name
implies, this clocks is 26 MHz, not 260 MHz.
Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")
Signed-off-by: David Lechner <[email protected]>
---
This fixes a bug in master, the intention is for this to go through
master. I have some other changes prepared (not sent yet) for the next
branch that will conflict with this. I assume the thing to do there is
wait for the next rc release when master gets merged back into next?
---
drivers/clk/mediatek/clk-mt8188.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8188.c
b/drivers/clk/mediatek/clk-mt8188.c
index 64aeaa5949f..5a38fb0fd49 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -98,7 +98,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000),
FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000),
FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000),
- FIXED_CLK0(CLK_TOP_CLK26M, 260000000),
+ FIXED_CLK0(CLK_TOP_CLK26M, 26000000),
FIXED_CLK0(CLK_TOP_CLK32K, 32000),
};
---
base-commit: f473a453b0c03d0042b4422de1d822274d2e2d4e
change-id: 20260304-clk-mtk-fix-mt8188-rates-9c733a841d56
Best regards,
--
David Lechner <[email protected]>
