Update DRAM chip type and density comment for 512 MiB DRAM settings for DH STM32MP13xx DHCOR DHSBC to match the chip on the SoM. No functional change.
Signed-off-by: Marek Vasut <[email protected]> --- Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: Tom Rini <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] --- arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi index 7b344541c3e..b464c04aa2b 100644 --- a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi @@ -3,13 +3,13 @@ * Copyright (C) 2025, DH electronics - All Rights Reserved * * STM32MP13xx DHSOM configuration - * 1x DDR3L 1Gb, 16-bit, 533MHz, Single Die Package in flyby topology. - * Reference used W631GU6MB15I from Winbond + * 1x DDR3L 4Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W634GU6RB11I from Winbond * * DDR type / Platform DDR3/3L * freq 533MHz * width 16 - * datasheet 0 = W631GU6MB15I / DDR3-1333 + * datasheet 0 = W634GU6RB11I / DDR3-1866 * DDR density 2 * timing mode optimized * address mapping : RBC -- 2.51.0
