From: Timur Tabi <ti...@freescale.com>
Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a
bank soft-reset after the bank was configured and enabled, even though enabling
a bank causes it to reset. Because the reset was required for multiple errata,
it was not properly enclosed in an #ifdef, and so was not removed with all the
other rev1 errata work-arounds.
Because this was the only SERDES bank soft-reset, there is no need to implement
a work-around for erratum SERDES-A003.
Signed-off-by: Timur Tabi <ti...@freescale.com>
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 741a0f8..e78d32d 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -729,9 +729,6 @@ void fsl_serdes_init(void)
}
#endif
- /* reset banks for errata */
- setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST);
-
wait_for_rstdone(bank);
}
--
1.7.3.4
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