Patch get form Rockchip downstream uboot repository.
Signed-off-by: WeiHao Li <ie...@outlook.com>
---
.../include/asm/arch-rockchip/cru_rk3368.h | 60 ++++++++++++
drivers/clk/rockchip/clk_rk3368.c | 94 +++++++++++++++++++
2 files changed, 154 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index ed2a612185..29f90454d4 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -80,6 +80,49 @@ enum {
PLL_RESET = 1,
PLL_RESET_MASK = GENMASK(5, 5),
+ /* CLKSEL1CON */
+ CORE_ACLK_DIV_SHIFT = 0,
+ CORE_ACLK_DIV_MASK = 0x1f << CORE_ACLK_DIV_SHIFT,
+ CORE_DBG_DIV_SHIFT = 8,
+ CORE_DBG_DIV_MASK = 0x1f << CORE_DBG_DIV_SHIFT,
+
+ CORE_CLK_PLL_SEL_SHIFT = 7,
+ CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
+ CORE_CLK_PLL_SEL_APLL = 0,
+ CORE_CLK_PLL_SEL_GPLL,
+ CORE_DIV_CON_SHIFT = 0,
+ CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
+
+ /* CLKSEL8CON */
+ PCLK_BUS_DIV_CON_SHIFT = 12,
+ PCLK_BUS_DIV_CON_MASK = 0x7 << PCLK_BUS_DIV_CON_SHIFT,
+ HCLK_BUS_DIV_CON_SHIFT = 8,
+ HCLK_BUS_DIV_CON_MASK = 0x3 << HCLK_BUS_DIV_CON_SHIFT,
+ CLK_BUS_PLL_SEL_CPLL = 0,
+ CLK_BUS_PLL_SEL_GPLL = 1,
+ CLK_BUS_PLL_SEL_SHIFT = 7,
+ CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT,
+ ACLK_BUS_DIV_CON_SHIFT = 0,
+ ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT,
+
+ /* CLKSEL9CON */
+ PCLK_PERI_DIV_CON_SHIFT = 12,
+ PCLK_PERI_DIV_CON_MASK = 0x3 << PCLK_PERI_DIV_CON_SHIFT,
+ HCLK_PERI_DIV_CON_SHIFT = 8,
+ HCLK_PERI_DIV_CON_MASK = 3 << HCLK_PERI_DIV_CON_SHIFT,
+ CLK_PERI_PLL_SEL_CPLL = 0,
+ CLK_PERI_PLL_SEL_GPLL,
+ CLK_PERI_PLL_SEL_SHIFT = 7,
+ CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT,
+ ACLK_PERI_DIV_CON_SHIFT = 0,
+ ACLK_PERI_DIV_CON_MASK = 0x1f,
+
+ /* CLKSEL10CON */
+ CLK_CRYPTO_DIV_CON_SHIFT = 14,
+ CLK_CRYPTO_DIV_CON_MASK = 0x3 << CLK_CRYPTO_DIV_CON_SHIFT,
+ PCLK_ALIVE_DIV_CON_SHIFT = 8,
+ PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
+
/* CLKSEL12_CON */
MCU_STCLK_DIV_SHIFT = 8,
MCU_STCLK_DIV_MASK = GENMASK(10, 8),
@@ -90,6 +133,23 @@ enum {
MCU_CLK_DIV_SHIFT = 0,
MCU_CLK_DIV_MASK = GENMASK(4, 0),
+ /* CLKSEL19_CON */
+ ACLK_VOP_PLL_SEL_SHIFT = 6,
+ ACLK_VOP_PLL_SEL_MASK = GENMASK(7, 6),
+ ACLK_VOP_PLL_SEL_CPLL = 0,
+ ACLK_VOP_PLL_SEL_GPLL = 1,
+ ACLK_VOP_DIV_SHIFT = 0,
+ ACLK_VOP_DIV_MASK = GENMASK(4, 0),
+
+ /* CLKSEL20_CON */
+ DCLK_VOP_PLL_SEL_SHIFT = 8,
+ DCLK_VOP_PLL_SEL_MASK = GENMASK(9, 8),
+ DCLK_VOP_PLL_SEL_CPLL = 0,
+ DCLK_VOP_PLL_SEL_GPLL = 1,
+ DCLK_VOP_PLL_SEL_NPLL = 2,
+ DCLK_VOP_DIV_SHIFT = 0,
+ DCLK_VOP_DIV_MASK = GENMASK(7, 0),
+
/* CLKSEL_CON25 */
CLK_SARADC_DIV_CON_SHIFT = 8,
CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
diff --git a/drivers/clk/rockchip/clk_rk3368.c
b/drivers/clk/rockchip/clk_rk3368.c
index 6691801384..aba7f2cd47 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -451,6 +451,82 @@ static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru,
uint hz)
return rk3368_saradc_get_clk(cru);
}
+#if !IS_ENABLED(CONFIG_XPL_BUILD)
+static ulong rk3368_bus_get_clk(struct rk3368_cru *cru, ulong clk_id)
+{
+ u32 div, con, parent;
+
+ switch (clk_id) {
+ case ACLK_BUS:
+ con = readl(&cru->clksel_con[8]);
+ div = (con & ACLK_BUS_DIV_CON_MASK) >> ACLK_BUS_DIV_CON_SHIFT;
+ parent = rkclk_pll_get_rate(cru, GPLL);
+ break;
+ case HCLK_BUS:
+ con = readl(&cru->clksel_con[8]);
+ div = (con & HCLK_BUS_DIV_CON_MASK) >> HCLK_BUS_DIV_CON_SHIFT;
+ parent = rk3368_bus_get_clk(cru, ACLK_BUS);
+ break;
+ case PCLK_BUS:
+ case PCLK_PWM0:
+ case PCLK_PWM1:
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ con = readl(&cru->clksel_con[8]);
+ div = (con & PCLK_BUS_DIV_CON_MASK) >> PCLK_BUS_DIV_CON_SHIFT;
+ parent = rk3368_bus_get_clk(cru, ACLK_BUS);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3368_bus_set_clk(struct rk3368_cru *cru,
+ ulong clk_id, ulong hz)
+{
+ int src_clk_div;
+
+ /*
+ * select gpll as pd_bus bus clock source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ switch (clk_id) {
+ case ACLK_BUS:
+ src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz);
+ assert(src_clk_div - 1 < 31);
+ rk_clrsetreg(&cru->clksel_con[8],
+ CLK_BUS_PLL_SEL_MASK | ACLK_BUS_DIV_CON_MASK,
+ CLK_BUS_PLL_SEL_GPLL << CLK_BUS_PLL_SEL_SHIFT |
+ (src_clk_div - 1) << ACLK_BUS_DIV_CON_SHIFT);
+ break;
+ case HCLK_BUS:
+ src_clk_div = DIV_ROUND_UP(rk3368_bus_get_clk(cru,
+ ACLK_BUS),
+ hz);
+ assert(src_clk_div - 1 < 3);
+ rk_clrsetreg(&cru->clksel_con[8],
+ HCLK_BUS_DIV_CON_MASK,
+ (src_clk_div - 1) << HCLK_BUS_DIV_CON_SHIFT);
+ break;
+ case PCLK_BUS:
+ src_clk_div = DIV_ROUND_UP(rk3368_bus_get_clk(cru,
+ ACLK_BUS),
+ hz);
+ assert(src_clk_div - 1 < 3);
+ rk_clrsetreg(&cru->clksel_con[8],
+ PCLK_BUS_DIV_CON_MASK,
+ (src_clk_div - 1) << PCLK_BUS_DIV_CON_SHIFT);
+ break;
+ default:
+ printf("do not support this bus freq\n");
+ return -EINVAL;
+ }
+ return rk3368_bus_get_clk(cru, clk_id);
+}
+#endif
+
static ulong rk3368_clk_get_rate(struct clk *clk)
{
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -467,6 +543,17 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
case SCLK_SPI0 ... SCLK_SPI2:
rate = rk3368_spi_get_clk(priv->cru, clk->id);
break;
+#if !IS_ENABLED(CONFIG_XPL_BUILD)
+ case ACLK_BUS:
+ case HCLK_BUS:
+ case PCLK_BUS:
+ case PCLK_PWM0:
+ case PCLK_PWM1:
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ rate = rk3368_bus_get_clk(priv->cru, clk->id);
+ break;
+#endif
#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
case HCLK_SDMMC:
case HCLK_EMMC:
@@ -498,6 +585,13 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong
rate)
ret = rk3368_ddr_set_clk(priv->cru, rate);
break;
#endif
+#if !IS_ENABLED(CONFIG_XPL_BUILD)
+ case ACLK_BUS:
+ case HCLK_BUS:
+ case PCLK_BUS:
+ rate = rk3368_bus_set_clk(priv->cru, clk->id, rate);
+ break;
+#endif
#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
case HCLK_SDMMC:
case HCLK_EMMC:
--
2.39.5
