[PATCH 6/9] ddr: imx: Move reading LP CSRs outside "ddr_cfg_phy" function

[Peng Fan (OSS)]

From: Viorel Suman <viorel.su...@nxp.com>

Reading CSRs for low power use shall be done regardless
the way the PHY is configured, so move the call outside
"ddr_cfg_phy" function in order to be called for QuickBoot FW
also.

Signed-off-by: Viorel Suman <viorel.su...@nxp.com>
Signed-off-by: Peng Fan <peng....@nxp.com>
---
 drivers/ddr/imx/imx8m/ddr_init.c   | 4 ++++
 drivers/ddr/imx/imx9/ddr_init.c    | 4 ++++
 drivers/ddr/imx/phy/ddrphy_train.c | 4 ----
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index 
7fdcfee1d9c982d391fe0d20e373a66d71d26e23..3b942fd3986699f76c1417c10f205dcdd7792dd0
 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -396,6 +396,10 @@ int ddr_init(struct dram_timing_info *dram_timing)
 
        debug("DDRINFO: ddrphy config done\n");
 
+       /* save the ddr PHY trained CSR in memory for low power use */
+       ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr,
+                               dram_timing->ddrphy_trained_csr_num);
+
        /*
         * step14 CalBusy.0 =1, indicates the calibrator is actively
         * calibrating. Wait Calibrating done.
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 
42ba493ebca4d6efc5ee047dd3f049cebb24b69d..50c2dbd40084c6a4d750f628c5c1fc76fa017596
 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -385,6 +385,10 @@ int ddr_init(struct dram_timing_info *dram_timing)
        if (ret)
                return ret;
 
+       /* save the ddr PHY trained CSR in memory for low power use */
+       ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr,
+                               dram_timing->ddrphy_trained_csr_num);
+
        debug("DDRINFO: ddrphy config done\n");
 
        update_umctl2_rank_space_setting(dram_timing, dram_timing->fsp_msg_num 
- 1);
diff --git a/drivers/ddr/imx/phy/ddrphy_train.c 
b/drivers/ddr/imx/phy/ddrphy_train.c
index 
1a2d071d6f10f8e7482e7be8498e1c18578404ec..84a1a17734f4d2a90f3bf0a6e54b5ae4ed49bebd
 100644
--- a/drivers/ddr/imx/phy/ddrphy_train.c
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -89,9 +89,5 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
                dram_cfg++;
        }
 
-       /* save the ddr PHY trained CSR in memory for low power use */
-       ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr,
-                               dram_timing->ddrphy_trained_csr_num);
-
        return 0;
 }

-- 
2.35.3