[PATCH 4/9] ddr: imx9: Disable dynamic refresh rate when do mr operation

[Peng Fan (OSS)]

From: "haidong.zheng" <haidong.zh...@nxp.com>

On i.MX93/91, dynamic refresh rate should be disabled before doing any
MR read or write. Otherwise conflict may happen with read MR12/MR14 in
ddr_init.
We randomly meet DDR unstable with low drive mode frequencies and 1600MTS
DDR setting on iMX91. With this fix, the issue is gone.

Signed-off-by: haidong.zheng <haidong.zh...@nxp.com>
Tested-by: Ye Li <ye...@nxp.com>
Reviewed-by: Jacky Bai <ping....@nxp.com>
Signed-off-by: Peng Fan <peng....@nxp.com>
---
 drivers/ddr/imx/imx9/ddr_init.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 
5a134dda78a331c21d4a75b2369c5b9314028bbc..42ba493ebca4d6efc5ee047dd3f049cebb24b69d
 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -266,6 +266,11 @@ void update_umctl2_rank_space_setting(struct 
dram_timing_info *dram_timing, unsi
 u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 *mode_reg_val)
 {
        u32 temp;
+       u8 dyn_ref_rate_en = 0;
+
+       dyn_ref_rate_en = !!(readl(REG_DDR_SDRAM_CFG_3) & BIT(7));
+       if (dyn_ref_rate_en)
+               clrbits_le32(REG_DDR_SDRAM_CFG_3, BIT(7));
 
        writel(0x80000000, REG_DDR_SDRAM_MD_CNTL_2);
        temp = 0x80000000 | (chip_select << 28) | (mode_reg_num << 0);
@@ -281,12 +286,20 @@ u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 
*mode_reg_val)
        writel(0x0, REG_DDR_SDRAM_MPR4);
        writel(0x0, REG_DDR_SDRAM_MD_CNTL_2);
 
+       if (dyn_ref_rate_en)
+               setbits_le32(REG_DDR_SDRAM_CFG_3, BIT(7));
+
        return 0;
 }
 
 void ddrc_mrs(u32 cs_sel, u32 opcode, u32 mr)
 {
        u32 regval;
+       u8 dyn_ref_rate_en = 0;
+
+       dyn_ref_rate_en = !!(readl(REG_DDR_SDRAM_CFG_3) & BIT(7));
+       if (dyn_ref_rate_en)
+               clrbits_le32(REG_DDR_SDRAM_CFG_3, BIT(7));
 
        regval = (cs_sel << 28) | (opcode << 6) | (mr);
        writel(regval, REG_DDR_SDRAM_MD_CNTL);
@@ -294,6 +307,9 @@ void ddrc_mrs(u32 cs_sel, u32 opcode, u32 mr)
        while ((readl(REG_DDR_SDRAM_MD_CNTL) & 0x80000000) == 0x80000000)
                ;
        check_ddrc_idle();
+
+       if (dyn_ref_rate_en)
+               setbits_le32(REG_DDR_SDRAM_CFG_3, BIT(7));
 }
 
 u32 lpddr4_mr_read(u32 mr_rank, u32 mr_addr)

-- 
2.35.3