On 7/4/25 06:04, Venkatesh Yadav Abbarapu wrote:
Starting from 'commit <8077d296adff> ("spi: cadence-quadspi: Use STIG mode for all ops with small payload") the utilization of STIG mode has been implemented for read and write operations involving less than 8 bytes of data. However, following this commit, encountering timeout issues occurs when writing odd bytes of data in DDR mode, as indicated below: "jedec_spi_nor flash@0: flash operation timed out SF: 3 bytes @ 0x0 Written: ERROR -110" To resolve this issue, the number of bytes to write has been updated specifically for DDR mode. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhum...@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbar...@amd.com> --- Changes in v2: -Modified the logic from using modulus and changed to use "logical and" operator to check the odd bytes. --- drivers/spi/cadence_qspi_apb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index b579699d2eb..76569a8019b 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -554,6 +554,9 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, void *reg_base = priv->regbase; u8 opcode;+ if (priv->dtr)+ txlen += txlen & 1; + if (priv->dtr) opcode = op->cmd.opcode >> 8; else
Applied. M
