TI's AM64x SoC has a single instance of PCIe Controller namely PCIe0 which is a Cadence PCIe Controller. To support PCI Endpoint functionality with the PCIe0 instance of PCIe, enable the corresponding configs.
Signed-off-by: Hrushikesh Salunke <h-salu...@ti.com> --- configs/am64x_evm_a53_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 8f7d098f770..5c3b46d710f 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -144,6 +144,8 @@ CONFIG_TI_ICSSG_PRUETH=y CONFIG_NVME_PCI=y CONFIG_PCI_CONFIG_HOST_BRIDGE=y CONFIG_PCIE_CDNS_TI=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCIE_CDNS_TI_EP=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_PHY_CADENCE_TORRENT=y -- 2.34.1
