Hi,
> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapa...@altera.com>
> Sent: Tuesday, May 6, 2025 10:13 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> <tien.fong.c...@altera.com>; Meng, Tingting <tingting.m...@altera.com>;
> Tom Rini <tr...@konsulko.com>; Ravulapalli, Naresh Kumar
> <naresh.kumar.ravulapa...@altera.com>
> Subject: [PATCH 5/5] drivers: ddr: altera: Add ECC scrubbing with Dcache
> enabled
>
> Add ECC scrubbing with Dcache enabled to speed up the scrubbing time.
> Change the SDRAM region to writethrough before scrubbing and restore
> back to its original behavior after that. This is to avoid triggering of false
> double-bit error.
The term 'ECC scrubbing' can be misleading, as it typically refers to the
process of periodically reading memory, correcting any ECC-detectable errors,
and optionally writing the corrected data back.
However, based on the code changes, it appears that the operation in question
is actually a full memory initialization-writing zeros across the entire memory
to bring it into a known state and to generate the corresponding ECC data
before use.
>
> Signed-off-by: Naresh Kumar Ravulapalli
> <nareshkumar.ravulapa...@altera.com>
> Signed-off-by: Tien Fong Chee <tien.fong.c...@altera.com>
> ---
> drivers/ddr/altera/sdram_arria10.c | 62 ++++++++++++------------
> drivers/ddr/altera/sdram_soc32.c | 75 ++++++++++++++++++++++++++---
> -
> drivers/ddr/altera/sdram_soc32.h | 2 +-
> 3 files changed, 99 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/ddr/altera/sdram_arria10.c
> b/drivers/ddr/altera/sdram_arria10.c
> index 133d4604738..8f281b82765 100644
> --- a/drivers/ddr/altera/sdram_arria10.c
> +++ b/drivers/ddr/altera/sdram_arria10.c
> @@ -4,7 +4,6 @@
> * Copyright (C) 2025 Altera Corporation <www.altera.com>
> */
>
> -#include <cpu_func.h>
> #include <errno.h>
> #include <fdtdec.h>
> #include <init.h>
> @@ -23,11 +22,14 @@
> #include <linux/bitops.h>
> #include <linux/delay.h>
> #include <linux/kernel.h>
> +#include <linux/sizes.h>
>
> #include "sdram_soc32.h"
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#define PGTABLE_OFF 0x4000
> +
> static void sdram_mmr_init(void);
> static u64 sdram_size_calc(void);
>
> @@ -129,10 +131,10 @@ static int emif_reset(void)
> s2c = readl(DDR_REG_SEQ2CORE);
>
> debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x
> dst=%08x\n",
> - c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
> - readl(IO48_MMR_NIOS2_RESERVE1),
> - readl(IO48_MMR_NIOS2_RESERVE2),
> - readl(IO48_MMR_DRAMSTS));
> + c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
> + readl(IO48_MMR_NIOS2_RESERVE1),
> + readl(IO48_MMR_NIOS2_RESERVE2),
> + readl(IO48_MMR_DRAMSTS));
>
> if (s2c & SEQ2CORE_MASK) {
> ret = emif_clear();
> @@ -162,9 +164,9 @@ static int emif_reset(void)
> debug("emif_reset interrupt cleared\n");
>
> debug("nr0=%08x nr1=%08x nr2=%08x\n",
> - readl(IO48_MMR_NIOS2_RESERVE0),
> - readl(IO48_MMR_NIOS2_RESERVE1),
> - readl(IO48_MMR_NIOS2_RESERVE2));
> + readl(IO48_MMR_NIOS2_RESERVE0),
> + readl(IO48_MMR_NIOS2_RESERVE1),
> + readl(IO48_MMR_NIOS2_RESERVE2));
>
> return 0;
> }
> @@ -225,7 +227,7 @@ static u64 sdram_size_calc(void)
> (dramaddrw &
> IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
>
> size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
> - ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
> + ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
>
> debug("SDRAM size=%llu\n", size);
>
> @@ -264,7 +266,7 @@ static void sdram_mmr_init(void)
> if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
> update_value = readl(&socfpga_io48_mmr_base-
> >niosreserve0);
> writel(((update_value & 0xFF) >> 5),
> - &socfpga_ecc_hmc_base->ddrioctrl);
> + &socfpga_ecc_hmc_base->ddrioctrl);
> }
>
> ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
> @@ -352,11 +354,11 @@ static void sdram_mmr_init(void)
> (ctrlcfg0_cfg_ctrl_burst_len >> 2));
>
> io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
> - ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2
> + 15 +
> - (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
> - /* Up to here was in memory cycles so divide by 2 */
> - caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
> - caltim4_cfg_pch_to_valid);
> + ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK)
> + 2 + 15 +
> + (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
> + /* Up to here was in memory cycles so divide by 2 */
> + caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
> + caltim4_cfg_pch_to_valid);
>
> writel(((caltim0_cfg_act_to_act <<
>
> ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) | @@
> -414,23 +416,23 @@ static void sdram_mmr_init(void)
> /* Enable or disable the SDRAM ECC */
> if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
> setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
> -
> (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
> - ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK
> |
> - ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
> +
> (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
> +
> ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
> +
> ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
> clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
> -
> (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
> -
> ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
> +
> (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
> +
> ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
> setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
> -
> (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
> -
> ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
> +
> (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
> +
> ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
> } else {
> clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
> -
> (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
> - ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK
> |
> - ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
> +
> (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
> +
> ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
> +
> ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
> clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
> -
> (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
> -
> ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
> +
> (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
> +
> ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
> }
> }
The patch should be split into two
1: For alignment clean up
2: For improving the performance of full memory initialization with DCACHE on.
[...]
Best regards,
Tien Fong
