[PATCH 3/6] clk: qcom: Use setbits_le32() for qcom_gate_clk_en()

[Stephan Gerhold]

The other clock enable functions in clock-qcom.c use setbits_le32() to
read/modify/write the enable registers. Use the same for qcom_gate_clk_en()
to simplify the code a bit.

Signed-off-by: Stephan Gerhold <stephan.gerh...@linaro.org>
---
 drivers/clk/qcom/clock-qcom.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 
5018851725b03d1c55c6fc40934bd7bea6344da1..7a259db79342c31dfe85220c68c82197861ccdf6
 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -76,16 +76,13 @@ void clk_enable_vote_clk(phys_addr_t base, const struct 
vote_clk *vclk)
 
 int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
 {
-       u32 val;
        if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
                log_err("gcc@%#08llx: unknown clock ID %lu!\n",
                        priv->base, id);
                return -ENOENT;
        }
 
-       val = readl(priv->base + priv->data->clks[id].reg);
-       writel(val | priv->data->clks[id].en_val, priv->base + 
priv->data->clks[id].reg);
-
+       setbits_le32(priv->base + priv->data->clks[id].reg, 
priv->data->clks[id].en_val);
        return 0;
 }
 

-- 
2.47.2