[PATCH 2/6] clk: qcom: Move qcom_gate_clk_en() to C file

[Stephan Gerhold]

This avoids having to inline it separately into every single clock driver,
when U-Boot is built with support for multiple SoCs.

Signed-off-by: Stephan Gerhold <stephan.gerh...@linaro.org>
---
 drivers/clk/qcom/clock-qcom.c | 15 +++++++++++++++
 drivers/clk/qcom/clock-qcom.h | 15 +--------------
 2 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 
7687bbe6a23b436e4ddf3b29d1c910062961126d..5018851725b03d1c55c6fc40934bd7bea6344da1
 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -74,6 +74,21 @@ void clk_enable_vote_clk(phys_addr_t base, const struct 
vote_clk *vclk)
        } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
 }
 
+int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
+{
+       u32 val;
+       if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
+               log_err("gcc@%#08llx: unknown clock ID %lu!\n",
+                       priv->base, id);
+               return -ENOENT;
+       }
+
+       val = readl(priv->base + priv->data->clks[id].reg);
+       writel(val | priv->data->clks[id].en_val, priv->base + 
priv->data->clks[id].reg);
+
+       return 0;
+}
+
 #define APPS_CMD_RCGR_UPDATE BIT(0)
 
 /* Update clock command via CMD_RCGR */
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 
f43edea25253305b34e7d879624ea5ee1a751746..ee0347d9d86716c09e7f57b343f12b5908f8cb92
 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -107,19 +107,6 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, 
int div,
                      int source);
 void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
 
-static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned 
long id)
-{
-       u32 val;
-       if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
-               log_err("gcc@%#08llx: unknown clock ID %lu!\n",
-                       priv->base, id);
-               return -ENOENT;
-       }
-
-       val = readl(priv->base + priv->data->clks[id].reg);
-       writel(val | priv->data->clks[id].en_val, priv->base + 
priv->data->clks[id].reg);
-
-       return 0;
-}
+int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id);
 
 #endif

-- 
2.47.2