On Wed, Apr 16, 2025 at 05:38:30PM +0530, Hrushikesh Salunke wrote: > TI's AM64 SoC has single instance of PCIe Controller namely PCIe0 which > is Cadence PCIe Controller. To support PCIe functionality with PCIe0 > instance in Root-Complex mode enable corresponding configs. Also enable > configs to support NVMe over PCIe. > > Signed-off-by: Hrushikesh Salunke <h-salu...@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapa...@ti.com> > --- > configs/am64x_evm_a53_defconfig | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig > index c2ad1242d20..9fc95798ffb 100644 > --- a/configs/am64x_evm_a53_defconfig > +++ b/configs/am64x_evm_a53_defconfig > @@ -31,6 +31,7 @@ CONFIG_SPL_FS_FAT=y > CONFIG_SPL_LIBDISK_SUPPORT=y > CONFIG_SPL_SPI_FLASH_SUPPORT=y > CONFIG_SPL_SPI=y > +CONFIG_PCI=y > # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set > CONFIG_SPL_LOAD_FIT=y > CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 > @@ -70,6 +71,7 @@ CONFIG_CMD_DFU=y > CONFIG_CMD_GPT=y > CONFIG_CMD_I2C=y > CONFIG_CMD_MMC=y > +CONFIG_CMD_PCI=y > CONFIG_CMD_USB=y > CONFIG_CMD_USB_MASS_STORAGE=y > CONFIG_CMD_EFIDEBUG=y > @@ -135,6 +137,9 @@ CONFIG_PHY_TI_DP83869=y > CONFIG_PHY_FIXED=y > CONFIG_TI_AM65_CPSW_NUSS=y > CONFIG_TI_ICSSG_PRUETH=y > +CONFIG_NVME_PCI=y > +CONFIG_PCI_CONFIG_HOST_BRIDGE=y > +CONFIG_PCIE_CDNS_TI=y > CONFIG_PHY=y > CONFIG_SPL_PHY=y > CONFIG_PHY_CADENCE_TORRENT=y Regards, Siddharth.
