On Wed, Apr 16, 2025 at 05:38:29PM +0530, Hrushikesh Salunke wrote:
> TI's AM64 SoC has single instance of PCIe Controller namely PCIe0 which
> is Cadence PCIe Controller. Add support to configure PCIe0 in Root-
> Complex mode of operation.
>
> Signed-off-by: Hrushikesh Salunke <h-salu...@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapa...@ti.com>
> ---
> drivers/pci/pcie_cdns_ti.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c
> index e5bcc6eb53e..9d1d123a18c 100644
> --- a/drivers/pci/pcie_cdns_ti.c
> +++ b/drivers/pci/pcie_cdns_ti.c
> @@ -835,11 +835,21 @@ static const struct pcie_cdns_ti_data
> j7200_pcie_rc_data = {
> .max_lanes = 2,
> };
>
> +static const struct pcie_cdns_ti_data am64_pcie_rc_data = {
> + .mode = PCIE_MODE_RC,
> + .quirk_detect_quiet_flag = true,
> + .max_lanes = 1,
> +};
> +
> static const struct udevice_id pcie_cdns_ti_ids[] = {
> {
> .compatible = "ti,j7200-pcie-host",
> .data = (ulong)&j7200_pcie_rc_data,
> },
> + {
> + .compatible = "ti,am64-pcie-host",
> + .data = (ulong)&am64_pcie_rc_data,
> + },
> {},
> };
Regards,
Siddharth.
