On 2/26/25 23:15, Stephen Boyd wrote:
Coreboot sets up the DRAM, CPU, and devices before booting a payload, meaning we can parse the coreboot tables at boot for memory info when running as a payload. Use the memory descriptors from coreboot if the tables are present so that Snapdragon SoCs can run U-boot as a coreboot payload. Signed-off-by: Stephen Boyd <swb...@chromium.org>
Reviewed-by: Caleb Connolly <caleb.conno...@linaro.org>
--- arch/arm/mach-snapdragon/board.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 2ef936aab757..cb3df1c2adec 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -14,6 +14,7 @@ #include <asm/io.h> #include <asm/psci.h> #include <asm/system.h> +#include <cb_sysinfo.h> #include <dm/device.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> @@ -48,6 +49,10 @@ static struct {int dram_init(void){ +#ifdef CONFIG_SYS_COREBOOT + if (gd->arch.coreboot_table) + return coreboot_dram_init(); +#endif /* * gd->ram_base / ram_size have been setup already * in qcom_parse_memory(). @@ -81,8 +86,21 @@ static void qcom_configure_bi_dram(void) } }+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)+{ +#ifdef CONFIG_SYS_COREBOOT + if (gd->arch.coreboot_table) + return coreboot_board_get_usable_ram_top(total_size); +#endif + return gd->ram_top; +} + int dram_init_banksize(void) { +#ifdef CONFIG_SYS_COREBOOT + if (gd->arch.coreboot_table) + return coreboot_dram_init_banksize(); +#endif qcom_configure_bi_dram();return 0;
-- Caleb (they/them)
