On Wed, Mar 26, 2025 at 10:01 AM Miquel Raynal
<miquel.ray...@bootlin.com> wrote:
>
> These are all the clocks needed to get an LCD panel working, going
> through one of the LCDIF and the LDB. The media AXI and APB clocks are
> also described.
>
You might need to rebase off the 'next' branch. Marek V submitted a
bunch of clock changes that slightly tweak the way clocks are
registered and it impacts the parent-child stuff. I am not sure this
will apply cleanly anymore.
adam
> Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com>
> ---
> drivers/clk/imx/clk-imx8mp.c | 69
> ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index
> bad579f8d5e47fcf078c6ca25e651ddc00fcb30f..f3c8ecf3a2080e74e6a108b995fbdd3ea2aa7b91
> 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -14,7 +14,14 @@
>
> #include "clk.h"
>
> +#if CONFIG_IS_ENABLED(VIDEO)
> +static u32 share_count_media;
> +#endif
> +
> static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy",
> "dummy", };
> +#if CONFIG_IS_ENABLED(VIDEO)
> +static const char * const video_pll1_bypass_sels[] = {"video_pll1",
> "video_pll1_ref_sel", };
> +#endif
> static const char * const dram_pll_bypass_sels[] = {"dram_pll",
> "dram_pll_ref_sel", };
> static const char * const arm_pll_bypass_sels[] = {"arm_pll",
> "arm_pll_ref_sel", };
> static const char * const sys_pll1_bypass_sels[] = {"sys_pll1",
> "sys_pll1_ref_sel", };
> @@ -31,6 +38,12 @@ static const char * const imx8mp_hsio_axi_sels[] =
> {"osc_24m", "sys_pll2_500m",
> "sys_pll2_100m",
> "sys_pll2_200m", "clk_ext2",
> "clk_ext4",
> "audio_pll2_out", };
>
> +#if CONFIG_IS_ENABLED(VIDEO)
> +static const char * const imx8mp_media_isp_sels[] = {"clock-osc-24m",
> "sys_pll2_1000m", "sys_pll1_800m",
> + "sys_pll3_out",
> "sys_pll1_400m", "audio_pll2_out",
> + "clk_ext1",
> "sys_pll2_500m", };
> +#endif
> +
> static const char * const imx8mp_main_axi_sels[] = {"osc_24m",
> "sys_pll2_333m", "sys_pll1_800m",
> "sys_pll2_250m",
> "sys_pll2_1000m", "audio_pll1_out",
> "video_pll1_out",
> "sys_pll1_100m",};
> @@ -43,6 +56,16 @@ static const char * const imx8mp_nand_usdhc_sels[] =
> {"osc_24m", "sys_pll1_266m"
> "sys_pll2_200m",
> "sys_pll1_133m", "sys_pll3_out",
> "sys_pll2_250m",
> "audio_pll1_out", };
>
> +#if CONFIG_IS_ENABLED(VIDEO)
> +static const char * const imx8mp_media_axi_sels[] = {"clock-osc-24m",
> "sys_pll2_1000m", "sys_pll1_800m",
> + "sys_pll3_out",
> "sys_pll1_40m", "audio_pll2_out",
> + "clk_ext1",
> "sys_pll2_500m", };
> +
> +static const char * const imx8mp_media_apb_sels[] = {"clock-osc-24m",
> "sys_pll2_125m", "sys_pll1_800m",
> + "sys_pll3_out", "sys_pll1_40m",
> "audio_pll2_out",
> + "clk_ext1", "sys_pll1_133m", };
> +#endif
> +
> static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m",
> "sys_pll3_out",
> "sys_pll2_1000m",
> "sys_pll2_500m", "audio_pll1_out",
> "video_pll1_out",
> "audio_pll2_out", };
> @@ -175,6 +198,17 @@ static const char * const imx8mp_usdhc3_sels[] =
> {"osc_24m", "sys_pll1_400m", "s
> "sys_pll2_500m",
> "sys_pll3_out", "sys_pll1_266m",
> "audio_pll2_out",
> "sys_pll1_100m", };
>
> +#if CONFIG_IS_ENABLED(VIDEO)
> +static const char * const imx8mp_media_disp_pix_sels[] = {"clock-osc-24m",
> "video_pll1_out", "audio_pll2_out",
> + "audio_pll1_out",
> "sys_pll1_800m",
> + "sys_pll2_1000m",
> "sys_pll3_out", "clk_ext4", };
> +
> +static const char * const imx8mp_media_ldb_sels[] = {"clock-osc-24m",
> "sys_pll2_333m", "sys_pll2_100m",
> + "sys_pll1_800m",
> "sys_pll2_1000m",
> + "clk_ext2",
> "audio_pll2_out",
> + "video_pll1_out", };
> +#endif
> +
> static const char * const imx8mp_enet_ref_sels[] = {"osc_24m",
> "sys_pll2_125m", "sys_pll2_50m",
> "sys_pll2_100m",
> "sys_pll1_160m", "audio_pll1_out",
> "video_pll1_out",
> "clk_ext4", };
> @@ -199,12 +233,19 @@ static int imx8mp_clk_probe(struct udevice *dev)
>
> clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
>
> +#if CONFIG_IS_ENABLED(VIDEO)
> + clk_dm(IMX8MP_VIDEO_PLL1_REF_SEL, imx_clk_mux(dev,
> "video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels,
> ARRAY_SIZE(pll_ref_sels)));
> +#endif
> clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux(dev, "dram_pll_ref_sel",
> base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux(dev, "arm_pll_ref_sel",
> base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux(dev, "sys_pll1_ref_sel",
> base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux(dev, "sys_pll2_ref_sel",
> base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
> clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux(dev, "sys_pll3_ref_sel",
> base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
>
> +#if CONFIG_IS_ENABLED(VIDEO)
> + clk_dm(IMX8MP_VIDEO_PLL1, imx_clk_pll14xx("video_pll1",
> "video_pll1_ref_sel", base + 0x28,
> + &imx_1443x_pll));
> +#endif
> clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll",
> "dram_pll_ref_sel", base + 0x50,
> &imx_1443x_dram_pll));
> clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
> base + 0x84,
> @@ -216,12 +257,18 @@ static int imx8mp_clk_probe(struct udevice *dev)
> clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3",
> "sys_pll3_ref_sel", base + 0x114,
> &imx_1416x_pll));
>
> +#if CONFIG_IS_ENABLED(VIDEO)
> + clk_dm(IMX8MP_VIDEO_PLL1_BYPASS, imx_clk_mux_flags(dev,
> "video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels,
> ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT));
> +#endif
> clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags(dev,
> "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels,
> ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
> clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags(dev,
> "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels,
> ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
> clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags(dev,
> "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels,
> ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
> clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags(dev,
> "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels,
> ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
> clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags(dev,
> "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels,
> ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
>
> +#if CONFIG_IS_ENABLED(VIDEO)
> + clk_dm(IMX8MP_VIDEO_PLL1_OUT, imx_clk_gate(dev, "video_pll1_out",
> "video_pll1_bypass", base + 0x28, 13));
> +#endif
> clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate(dev, "dram_pll_out",
> "dram_pll_bypass", base + 0x50, 13));
> clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate(dev, "arm_pll_out",
> "arm_pll_bypass", base + 0x84, 11));
> clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate(dev, "sys_pll1_out",
> "sys_pll1_bypass", base + 0x94, 11));
> @@ -267,13 +314,23 @@ static int imx8mp_clk_probe(struct udevice *dev)
> clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2(dev, "arm_a53_div",
> "arm_a53_cg", base + 0x8000, 0, 3));
>
> clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite(dev, "hsio_axi",
> imx8mp_hsio_axi_sels, base + 0x8380));
> +#if CONFIG_IS_ENABLED(VIDEO)
> + clk_dm(IMX8MP_CLK_MEDIA_ISP, imx8m_clk_composite(dev, "media_isp",
> imx8mp_media_isp_sels, base + 0x8400));
> +#endif
> clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical(dev,
> "main_axi", imx8mp_main_axi_sels, base + 0x8800));
> clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical(dev,
> "enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
> clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical(dev,
> "nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
> +#if CONFIG_IS_ENABLED(VIDEO)
> + clk_dm(IMX8MP_CLK_MEDIA_AXI, imx8m_clk_composite(dev, "media_axi",
> imx8mp_media_axi_sels, base + 0x8a00));
> + clk_dm(IMX8MP_CLK_MEDIA_APB, imx8m_clk_composite(dev, "media_apb",
> imx8mp_media_apb_sels, base + 0x8a80));
> +#endif
> clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical(dev, "noc",
> imx8mp_noc_sels, base + 0x8d00));
> clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical(dev, "noc_io",
> imx8mp_noc_io_sels, base + 0x8d80));
>
> clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb_root",
> imx8mp_ahb_sels, base + 0x9000));
> +#if CONFIG_IS_ENABLED(VIDEO)
> + clk_dm(IMX8MP_CLK_MEDIA_DISP2_PIX, imx8m_clk_composite(dev,
> "media_disp2_pix", imx8mp_media_disp_pix_sels, base + 0x9300));
> +#endif
>
> clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2(dev, "ipg_root",
> "ahb_root", base + 0x9080, 0, 1));
>
> @@ -312,6 +369,10 @@ static int imx8mp_clk_probe(struct udevice *dev)
>
> clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite(dev, "wdog",
> imx8mp_wdog_sels, base + 0xb900));
> clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite(dev, "usdhc3",
> imx8mp_usdhc3_sels, base + 0xbc80));
> +#if CONFIG_IS_ENABLED(VIDEO)
> + clk_dm(IMX8MP_CLK_MEDIA_DISP1_PIX, imx8m_clk_composite(dev,
> "media_disp1_pix", imx8mp_media_disp_pix_sels, base + 0xbe00));
> + clk_dm(IMX8MP_CLK_MEDIA_LDB, imx8m_clk_composite(dev, "media_ldb",
> imx8mp_media_ldb_sels, base + 0xbf00));
> +#endif
>
> clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor(dev,
> "dram_alt_root", "dram_alt", 1, 4));
> clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk",
> base + 0x9800, 24, 1, imx8mp_dram_core_sels,
> ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
> @@ -355,6 +416,14 @@ static int imx8mp_clk_probe(struct udevice *dev)
> clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4(dev, "wdog2_root_clk",
> "wdog", base + 0x4540, 0));
> clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4(dev, "wdog3_root_clk",
> "wdog", base + 0x4550, 0));
> clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4(dev, "hsio_root_clk",
> "ipg_root", base + 0x45c0, 0));
> +#if CONFIG_IS_ENABLED(VIDEO)
> + clk_dm(IMX8MP_CLK_MEDIA_APB_ROOT, imx_clk_gate2_shared2(dev,
> "media_apb_root_clk", "media_apb", base + 0x45d0, 0, &share_count_media));
> + clk_dm(IMX8MP_CLK_MEDIA_AXI_ROOT, imx_clk_gate2_shared2(dev,
> "media_axi_root_clk", "media_axi", base + 0x45d0, 0, &share_count_media));
> + clk_dm(IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT, imx_clk_gate2_shared2(dev,
> "media_disp1_pix_root_clk", "media_disp1_pix", base + 0x45d0, 0,
> &share_count_media));
> + clk_dm(IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT, imx_clk_gate2_shared2(dev,
> "media_disp2_pix_root_clk", "media_disp2_pix", base + 0x45d0, 0,
> &share_count_media));
> + clk_dm(IMX8MP_CLK_MEDIA_LDB_ROOT, imx_clk_gate2_shared2(dev,
> "media_ldb_root_clk", "media_ldb", base + 0x45d0, 0, &share_count_media));
> + clk_dm(IMX8MP_CLK_MEDIA_ISP_ROOT, imx_clk_gate2_shared2(dev,
> "media_isp_root_clk", "media_isp", base + 0x45d0, 0, &share_count_media));
> +#endif
>
> clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4(dev, "usdhc3_root_clk",
> "usdhc3", base + 0x45e0, 0));
>
>
> --
> 2.48.1
>
