Since the SoC and board DT are already available in dts/upstream,
add the difference from upstream DTS to at91-sam9x75_curiosity-u-boot.dtsi

Signed-off-by: Manikandan Muralidharan <manikanda...@microchip.com>
---
 .../dts/at91-sam9x75_curiosity-u-boot.dtsi    | 107 ++++++++++++++++++
 1 file changed, 107 insertions(+)
 create mode 100644 arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi

diff --git a/arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi 
b/arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi
new file mode 100644
index 00000000000..dc4fef950ec
--- /dev/null
+++ b/arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x75_curiosity-u-boot.dtsi - Device Tree file for SAM9X75
+ * CURIOSITY board.
+ *
+ * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Manikandan Muralidharan <manikanda...@microchip.com>
+ */
+
+/ {
+       cpus {
+               cpu@0 {
+                       clocks = <&pmc PMC_TYPE_CORE 25>, <&pmc PMC_TYPE_CORE 
17>, <&main_xtal>;
+                       clock-names = "cpu", "master", "xtal";
+               };
+       };
+
+       clocks {
+               slow_rc_osc: slow_rc_osc {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <18500>;
+               };
+
+               main_rc: main_rc {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <12000000>;
+               };
+       };
+
+       ahb {
+               bootph-all;
+
+               apb {
+                       bootph-all;
+
+                       pinctrl {
+                               bootph-all;
+                       };
+               };
+       };
+
+       chosen {
+               bootph-all;
+       };
+};
+
+&clk32k {
+       bootph-all;
+       clocks = <&slow_rc_osc>, <&slow_xtal>;
+};
+
+&dbgu {
+       bootph-all;
+};
+
+&gmac {
+       compatible = "microchip,sam9x7-gem", "cdns,sama7g5-gem";
+};
+
+&main_rc {
+       bootph-all;
+};
+
+&main_xtal {
+       bootph-all;
+};
+
+&pinctrl_dbgu_default {
+       bootph-all;
+};
+
+&pinctrl_sdmmc0_default {
+       bootph-all;
+};
+
+&pioA {
+       bootph-all;
+};
+
+&pioB {
+       bootph-all;
+};
+
+&pit64b0 {
+       bootph-all;
+};
+
+&pmc {
+       bootph-all;
+       clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>, <&main_rc>;
+       clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
+};
+
+&sdmmc0 {
+       bootph-all;
+};
+
+&slow_xtal {
+       bootph-all;
+};
+
+&slow_rc_osc {
+       bootph-all;
+};
-- 
2.25.1

Reply via email to