On Tue, May 31, 2011 at 04:22:49PM +0100, Phil Edworthy wrote:
> The rsk7264 (also know as rsk2+sh7264) is an SH2A based board
> with 64MB NAND flash and 64MB SDRAM. It is very similar to the
> rsk7203 board.
>
> Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com>
> Cc: Nobuhiro Iwamatsu <iwama...@nigauri.org>
> ---
> arch/sh/cpu/sh2/cpu.c | 7 +
> arch/sh/include/asm/cpu_sh2.h | 2 +
> arch/sh/include/asm/cpu_sh7264.h | 41 +++++++
> board/renesas/rsk7264/Makefile | 32 +++++
> board/renesas/rsk7264/lowlevel_init.S | 212
> +++++++++++++++++++++++++++++++++
> board/renesas/rsk7264/rsk7264.c | 72 +++++++++++
> boards.cfg | 1 +
> drivers/serial/serial_sh.h | 5 +-
> include/configs/rsk7264.h | 99 +++++++++++++++
> 9 files changed, 470 insertions(+), 1 deletions(-)
> create mode 100644 arch/sh/include/asm/cpu_sh7264.h
> create mode 100644 board/renesas/rsk7264/Makefile
> create mode 100644 board/renesas/rsk7264/lowlevel_init.S
> create mode 100644 board/renesas/rsk7264/rsk7264.c
> create mode 100644 include/configs/rsk7264.h
>
> diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
> index 6bbedd9..70c7258 100644
> --- a/arch/sh/cpu/sh2/cpu.c
> +++ b/arch/sh/cpu/sh2/cpu.c
> @@ -33,6 +33,9 @@
> #define scif0_enable() do {\
> writeb(readb(STBCR4) & ~0x80, STBCR4);\
> } while (0)
> +#define scif3_enable() do {\
> + writeb(readb(STBCR4) & ~0x10, STBCR4);\
> + } while (0)
>
> int checkcpu(void)
> {
> @@ -47,7 +50,11 @@ int checkcpu(void)
> int cpu_init(void)
> {
> /* SCIF enable */
> +#if defined(RSK7264)
> + scif3_enable();
> +#else
> scif0_enable();
> +#endif
> /* CMT clock enable */
> cmt_clock_enable() ;
> return 0;
Please don't depends target board (RSK7264).
Please use CONFIG_CONS_SCIF3.
> diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
> index 8bc9bc6..767e189 100644
> --- a/arch/sh/include/asm/cpu_sh2.h
> +++ b/arch/sh/include/asm/cpu_sh2.h
> @@ -33,6 +33,8 @@
And you forget to update MAINTAINERS file.
Please add you to this file.
Best regards,
Nobuhiro
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