Add Clock Controller node for EN7581 SoC to correctly expose supported clock for any user in the SoC.
Signed-off-by: Christian Marangi <ansuels...@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delre...@collabora.com> Link: https://lore.kernel.org/r/20250105150328.15172-1-ansuels...@gmail.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delre...@collabora.com> [ upstream commit: 7693017580e9be839fa5f27130bb6500f3597595 ] --- dts/upstream/src/arm64/airoha/en7581.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/dts/upstream/src/arm64/airoha/en7581.dtsi b/dts/upstream/src/arm64/airoha/en7581.dtsi index 55eb1762fb1..f584409e72c 100644 --- a/dts/upstream/src/arm64/airoha/en7581.dtsi +++ b/dts/upstream/src/arm64/airoha/en7581.dtsi @@ -2,6 +2,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/en7523-clk.h> / { interrupt-parent = <&gic>; @@ -142,6 +143,13 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + scuclk: clock-controller@1fa20000 { + compatible = "airoha,en7581-scu"; + reg = <0x0 0x1fb00000 0x0 0x970>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart1: serial@1fbf0000 { compatible = "ns16550"; reg = <0x0 0x1fbf0000 0x0 0x30>; -- 2.48.1
