-----Original Message-----
From: alif.zakuan.yusla...@intel.com <alif.zakuan.yusla...@intel.com>
Sent: Tuesday, February 18, 2025 4:35 PM
To: u-boot@lists.denx.de
Cc: Marek Vasut <ma...@denx.de>; Simon Goldschmidt
<simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong <tien.fong.c...@altera.com>;
Yuslaimi, Alif Zakuan <alif.zakuan.yusla...@altera.com>; Meng, Tingting
<tingting.m...@altera.com>; Ng, Boon Khai <boon.khai...@altera.com>; Hea, Kok
Kiang <kok.kiang....@altera.com>; Alif Zakuan Yuslaimi
<alif.zakuan.yusla...@intel.com>
Subject: [PATCH v2 03/26] drivers: clk: agilex5: Configure intosc as boot_clk
source
From: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@intel.com>
Some customers prefer to minimize the use of external oscillators, especially
when using the FPGA first configuration mode.
By enabling the configuration of the HPS internal oscillator as the boot_clk
source instead of the default external oscillator,
(HPS_OSC_CLK) in non-secure boot scenarios, this allows them to eliminate the
need for an additional oscillator device and a dedicated HPS pin, simplifying
board layout and routing.
Signed-off-by: Tingting Meng <tingting.m...@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@altera.com>
---
drivers/clk/altera/clk-agilex5.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c
index 716c71598bc..dfc25ac6787 100644
--- a/drivers/clk/altera/clk-agilex5.c
+++ b/drivers/clk/altera/clk-agilex5.c
@@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
-#include <clk-uclass.h>
#include <config.h>
-#include <errno.h>
-#include <dm.h>
#include <log.h>
+#include <dm.h>
+#include <errno.h>
#include <stdarg.h>
#include <stdio.h>
#include <time.h>
@@ -23,9 +23,14 @@
#include <linux/types.h>
#include <asm/arch/clock_manager.h>
#include <dt-bindings/clock/agilex5-clock.h>
+#include <wait_bit.h>
+#include <clk-uclass.h>
DECLARE_GLOBAL_DATA_PTR;
+#define CLKMGR_CTRL_SWCTRLBTCLKEN_MASK BIT(8)
+#define CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK BIT(9)
+
struct socfpga_clk_plat {
void __iomem *regs;
};
@@ -264,9 +269,14 @@ static void clk_basic_init(struct udevice *dev,
CM_REG_READL(plat, CLKMGR_CTRL) &
~CLKMGR_CTRL_BOOTMODE);
} else {
#ifdef CONFIG_XPL_BUILD
- /* Always force clock manager into boot mode before any
configuration */
- clk_write_ctrl(plat,
- CM_REG_READL(plat, CLKMGR_CTRL) |
CLKMGR_CTRL_BOOTMODE);
+ /*
+ * Configure HPS Internal Oscillator as default boot_clk source,
+ * always force clock manager into boot mode before any
configuration
+ */
+ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) |
+ CLKMGR_CTRL_BOOTMODE |
+ CLKMGR_CTRL_SWCTRLBTCLKEN_MASK |
+ CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK);
#else
/* Skip clock configuration in SSBL if it's not in boot mode */
if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
--
2.25.1
Reviewed-by: Tien Fong Chee <tien.fong.c...@altera.com>
Best regards,
Tien Fong
