[PATCH 09/13] net: fsl_enetc: Introduce driver data

[Marek Vasut]

Introduce driver data for each PCI device. The driver data carry
offsets of registers which differ between different SoCs.

Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: Alice Guo <alice....@nxp.com>
Cc: Ilias Apalodimas <ilias.apalodi...@linaro.org>
Cc: Jerome Forissier <jerome.foriss...@linaro.org>
Cc: Joe Hershberger <joe.hershber...@ni.com>
Cc: Markus Gothe <markus.go...@genexis.eu>
Cc: Peng Fan <peng....@nxp.com>
Cc: Ramon Fried <rfried....@gmail.com>
Cc: Robert Marko <robert.ma...@sartura.hr>
Cc: Romain Naour <romain.na...@smile.fr>
Cc: Simon Glass <s...@chromium.org>
Cc: Tim Harvey <thar...@gateworks.com>
Cc: Tom Rini <tr...@konsulko.com>
Cc: Ye Li <ye...@nxp.com>
Cc: u-boot@lists.denx.de
---
 drivers/net/fsl_enetc.c | 13 ++++++++++++-
 drivers/net/fsl_enetc.h |  9 +++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index 532a367c241..c92626a8782 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -786,8 +786,19 @@ U_BOOT_DRIVER(eth_enetc_ls) = {
        .plat_auto      = sizeof(struct eth_pdata),
 };
 
+static const struct enetc_data enetc_data_ls = {
+       .reg_offset_pmr         = ENETC_PMR_OFFSET_LS,
+       .reg_offset_psipmar     = ENETC_PSIPMARn_OFFSET_LS,
+       .reg_offset_pcapr       = ENETC_PCAPR_OFFSET_LS,
+       .reg_offset_psicfgr     = ENETC_PSICFGR_OFFSET_LS,
+       .reg_offset_mac         = ENETC_PM_OFFSET_LS,
+};
+
 static struct pci_device_id enetc_ids_ls[] = {
-       { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
+       {
+               PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH),
+               .driver_data = (ulong)&enetc_data_ls,
+       },
        {}
 };
 
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h
index 15408b669b4..b815474c246 100644
--- a/drivers/net/fsl_enetc.h
+++ b/drivers/net/fsl_enetc.h
@@ -168,6 +168,15 @@ struct enetc_priv {
        struct phy_device *phy;
 };
 
+struct enetc_data {
+       /* Register layout offsets */
+       u16                     reg_offset_pmr;
+       u16                     reg_offset_psipmar;
+       u16                     reg_offset_pcapr;
+       u16                     reg_offset_psicfgr;
+       u16                     reg_offset_mac;
+};
+
 /* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */
 #define ENETC_PCS_PHY_ADDR     0
 
-- 
2.45.2