Split register accessors to the port base/station interface/port/mac
registers as those are at different offsets on different SoCs. This
is a preparatory patch which will allow addition of adjusted offsets
for new SoCs easily.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: Alice Guo <alice....@nxp.com>
Cc: Ilias Apalodimas <ilias.apalodi...@linaro.org>
Cc: Jerome Forissier <jerome.foriss...@linaro.org>
Cc: Joe Hershberger <joe.hershber...@ni.com>
Cc: Markus Gothe <markus.go...@genexis.eu>
Cc: Peng Fan <peng....@nxp.com>
Cc: Ramon Fried <rfried....@gmail.com>
Cc: Robert Marko <robert.ma...@sartura.hr>
Cc: Romain Naour <romain.na...@smile.fr>
Cc: Simon Glass <s...@chromium.org>
Cc: Tim Harvey <thar...@gateworks.com>
Cc: Tom Rini <tr...@konsulko.com>
Cc: Ye Li <ye...@nxp.com>
Cc: u-boot@lists.denx.de
---
drivers/net/fsl_enetc.c | 68 +++++++++++++++++++++++++++++++----------
drivers/net/fsl_enetc.h | 25 +++++++++------
2 files changed, 67 insertions(+), 26 deletions(-)
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index ace1069efd9..532a367c241 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -56,14 +56,52 @@ static void enetc_write(struct enetc_priv *priv, u32 off,
u32 val)
enetc_write_reg(priv->regs_base + off, val);
}
+/* base port register accessors */
+static void enetc_write_pmr(struct enetc_priv *priv, u32 val)
+{
+ const u32 off = ENETC_PMR + ENETC_PMR_OFFSET_LS;
+
+ enetc_write_reg(priv->port_regs + off, val);
+}
+
+static void enetc_write_psipmar(struct enetc_priv *priv, int n, u32 val)
+{
+ const u32 off = (n ? ENETC_PSIPMAR1 : ENETC_PSIPMAR0) +
+ ENETC_PSIPMARn_OFFSET_LS;
+
+ enetc_write_reg(priv->port_regs + off, val);
+}
+
+/* port station register accessors */
+static void enetc_write_psicfgr(struct enetc_priv *priv, int port, u32 val)
+{
+ const u32 off = ENETC_PSICFGR(port, ENETC_PSICFGR_SHIFT_LS) +
+ ENETC_PSICFGR_OFFSET_LS;
+
+ enetc_write_reg(priv->port_regs + off, val);
+}
+
/* port register accessors */
-static u32 enetc_read_port(struct enetc_priv *priv, u32 off)
+static u32 enetc_read_pcapr_mdio(struct enetc_priv *priv)
+{
+ const u32 off = ENETC_PCAPR0 + ENETC_PCAPR_OFFSET_LS;
+ u32 reg = enetc_read_reg(priv->port_regs + off);
+
+ return reg & ENETC_PCAPRO_MDIO;
+}
+
+/* MAC port register accessors */
+static u32 enetc_read_mac_port(struct enetc_priv *priv, u32 off)
{
+ off += ENETC_PM_OFFSET_LS;
+
return enetc_read_reg(priv->port_regs + off);
}
-static void enetc_write_port(struct enetc_priv *priv, u32 off, u32 val)
+static void enetc_write_mac_port(struct enetc_priv *priv, u32 off, u32 val)
{
+ off += ENETC_PM_OFFSET_LS;
+
enetc_write_reg(priv->port_regs + off, val);
}
@@ -234,7 +272,7 @@ static void enetc_init_rgmii(struct udevice *dev, struct
phy_device *phydev)
struct enetc_priv *priv = dev_get_priv(dev);
u32 old_val, val;
- old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE);
+ old_val = val = enetc_read_mac_port(priv, ENETC_PM_IF_MODE);
/* disable unreliable RGMII in-band signaling and force the MAC into
* the speed negotiated by the PHY.
@@ -260,7 +298,7 @@ static void enetc_init_rgmii(struct udevice *dev, struct
phy_device *phydev)
if (val == old_val)
return;
- enetc_write_port(priv, ENETC_PM_IF_MODE, val);
+ enetc_write_mac_port(priv, ENETC_PM_IF_MODE, val);
}
/* set up MAC configuration for the given interface type */
@@ -280,9 +318,9 @@ static void enetc_setup_mac_iface(struct udevice *dev,
case PHY_INTERFACE_MODE_USXGMII:
case PHY_INTERFACE_MODE_10GBASER:
/* set ifmode to (US)XGMII */
- if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
+ if_mode = enetc_read_mac_port(priv, ENETC_PM_IF_MODE);
if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
- enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
+ enetc_write_mac_port(priv, ENETC_PM_IF_MODE, if_mode);
break;
};
}
@@ -313,7 +351,7 @@ static void enetc_start_pcs(struct udevice *dev)
struct enetc_priv *priv = dev_get_priv(dev);
/* register internal MDIO for debug purposes */
- if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
+ if (enetc_read_pcapr_mdio(priv)) {
priv->imdio.read = enetc_mdio_read;
priv->imdio.write = enetc_mdio_write;
priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
@@ -472,8 +510,8 @@ static int enetc_write_hwaddr(struct udevice *dev)
u16 lower = *(const u16 *)(addr + 4);
u32 upper = *(const u32 *)addr;
- enetc_write_port(priv, ENETC_PSIPMAR0, upper);
- enetc_write_port(priv, ENETC_PSIPMAR1, lower);
+ enetc_write_psipmar(priv, 0, upper);
+ enetc_write_psipmar(priv, 1, lower);
return 0;
}
@@ -482,18 +520,16 @@ static int enetc_write_hwaddr(struct udevice *dev)
static void enetc_enable_si_port(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
- u32 val;
/* set Rx/Tx BDR count */
- val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
- val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
- enetc_write_port(priv, ENETC_PSICFGR(0), val);
+ enetc_write_psicfgr(priv, 0, ENETC_PSICFGR_SET_BDR(ENETC_RX_BDR_CNT,
+ ENETC_TX_BDR_CNT));
/* set Rx max frame size */
- enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
+ enetc_write_mac_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
/* enable MAC port */
- enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
+ enetc_write_mac_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
/* enable port */
- enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
+ enetc_write_pmr(priv, ENETC_PMR_SI0_EN);
/* set SI cache policy */
enetc_write(priv, ENETC_SICAR0,
ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h
index da7414cbe99..15408b669b4 100644
--- a/drivers/net/fsl_enetc.h
+++ b/drivers/net/fsl_enetc.h
@@ -57,24 +57,29 @@ enum enetc_bdr_type {TX, RX};
#define ENETC_PORT_REGS_OFF 0x10000
/* Port registers */
+#define ENETC_PMR_OFFSET_LS 0x0000
#define ENETC_PMR 0x0000
#define ENETC_PMR_SI0_EN BIT(16)
#define ENETC_PSIPMMR 0x0018
-#define ENETC_PSIPMAR0 0x0100
-#define ENETC_PSIPMAR1 0x0104
-#define ENETC_PCAPR0 0x0900
+#define ENETC_PSIPMARn_OFFSET_LS 0x0080
+#define ENETC_PSIPMAR0 0x0080
+#define ENETC_PSIPMAR1 0x0084
+#define ENETC_PCAPR_OFFSET_LS 0x0900
+#define ENETC_PCAPR0 0x0000
#define ENETC_PCAPRO_MDIO BIT(11)
-#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
-#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
-#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
+#define ENETC_PSICFGR_OFFSET_LS 0x0940
+#define ENETC_PSICFGR_SHIFT_LS 0x10
+#define ENETC_PSICFGR(n, s) ((n) * (s))
+#define ENETC_PSICFGR_SET_BDR(rx, tx) (((rx) << 16) | (tx))
/* MAC configuration */
-#define ENETC_PM_CC 0x8008
+#define ENETC_PM_OFFSET_LS 0x8000
+#define ENETC_PM_CC 0x0008
#define ENETC_PM_CC_DEFAULT 0x0810
#define ENETC_PM_CC_RX_TX_EN 0x8813
-#define ENETC_PM_MAXFRM 0x8014
+#define ENETC_PM_MAXFRM 0x0014
#define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
-#define ENETC_PM_IMDIO_BASE 0x8030
-#define ENETC_PM_IF_MODE 0x8300
+#define ENETC_PM_IMDIO_BASE 0x0030
+#define ENETC_PM_IF_MODE 0x0300
#define ENETC_PM_IF_MODE_RG BIT(2)
#define ENETC_PM_IF_MODE_AN_ENA BIT(15)
#define ENETC_PM_IFM_SSP_MASK GENMASK(14, 13)
--
2.45.2
